[U-Boot] [PATCH 1/2] ARM: tegra124: Clear IDDQ when enabling PLLC

[Nicolas Chauvet]

Tested-by: Nicolas Chauvet <kwizart at gmail.com>
Test-HW: jetson-tk1

Fix the issue on recent kernel

Nicolas (kwizart)

2015-09-08 11:38 GMT+02:00 Thierry Reding <thierry.reding at gmail.com>:

> From: Thierry Reding <treding at nvidia.com>
>
> Enabling a PLL while IDDQ is high. The Linux kernel checks for this
> condition and warns about it verbosely, so while this seems to work
> fine, fix it up according to the programming guidelines provided in
> the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup
> Sequence").
>
> Reported-by: Nicolas Chauvet <kwizart at gmail.com>
> Signed-off-by: Thierry Reding <treding at nvidia.com>
> ---
>  arch/arm/include/asm/arch-tegra124/clock.h | 3 +++
>  arch/arm/mach-tegra/tegra124/clock.c       | 5 +++++
>  2 files changed, 8 insertions(+)
>
> diff --git a/arch/arm/include/asm/arch-tegra124/clock.h
> b/arch/arm/include/asm/arch-tegra124/clock.h
> index e202cc5a7f46..ff99b9dfafda 100644
> --- a/arch/arm/include/asm/arch-tegra124/clock.h
> +++ b/arch/arm/include/asm/arch-tegra124/clock.h
> @@ -16,6 +16,9 @@
>  #define OSC_FREQ_SHIFT          28
>  #define OSC_FREQ_MASK           (0xF << OSC_FREQ_SHIFT)
>
> +/* CLK_RST_CONTROLLER_PLLC_MISC_0 */
> +#define PLLC_IDDQ                      (1 << 26)
> +
>  /* CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0 */
>  #define SOR0_CLK_SEL0                  (1 << 14)
>  #define SOR0_CLK_SEL1                  (1 << 15)
> diff --git a/arch/arm/mach-tegra/tegra124/clock.c
> b/arch/arm/mach-tegra/tegra124/clock.c
> index aa046e8950f7..1e71146236e9 100644
> --- a/arch/arm/mach-tegra/tegra124/clock.c
> +++ b/arch/arm/mach-tegra/tegra124/clock.c
> @@ -809,6 +809,11 @@ void clock_early_init(void)
>
>         tegra30_set_up_pllp();
>
> +       /* clear IDDQ before accessing any other PLLC registers */
> +       pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL];
> +       clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc,
> PLLC_IDDQ);
> +       udelay(2);
> +
>         /*
>          * PLLC output frequency set to 600Mhz
>          * PLLD output frequency set to 925Mhz
> --
> 2.5.0
>
>


-- 
-

Nicolas (kwizart)