[U-Boot] [PATCH v2 6/8] x86: galileo: Add PCIe root port IRQ routing

[Bin Meng]

Now we have enabled PCIe root port on Quark SoC, add its PIRQ
routing information in the device tree as well.

Signed-off-by: Bin Meng <bmeng.cn at gmail.com>
Acked-by: Simon Glass <sjg at chromium.org>
---

Changes in v2: None

 arch/x86/dts/galileo.dts | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts
index f119bf7..a4e1676 100644
--- a/arch/x86/dts/galileo.dts
+++ b/arch/x86/dts/galileo.dts
@@ -92,6 +92,18 @@
 				PCI_BDF(0, 21, 0) INTA PIRQE
 				PCI_BDF(0, 21, 1) INTB PIRQF
 				PCI_BDF(0, 21, 2) INTC PIRQG
+				PCI_BDF(0, 23, 0) INTA PIRQA
+				PCI_BDF(0, 23, 1) INTB PIRQB
+
+				/* PCIe root ports downstream interrupts */
+				PCI_BDF(1, 0, 0) INTA PIRQA
+				PCI_BDF(1, 0, 0) INTB PIRQB
+				PCI_BDF(1, 0, 0) INTC PIRQC
+				PCI_BDF(1, 0, 0) INTD PIRQD
+				PCI_BDF(2, 0, 0) INTA PIRQB
+				PCI_BDF(2, 0, 0) INTB PIRQC
+				PCI_BDF(2, 0, 0) INTC PIRQD
+				PCI_BDF(2, 0, 0) INTD PIRQA
 			>;
 		};
 	};
-- 
1.8.2.1