[U-Boot] [PATCH 04/14] net/fm: Add QSGMII PCS init

[Gong Qianyu]

From: Shaohui Xie <Shaohui.Xie at freescale.com>

QSGMII PCS needed to be programmed same as SGMII PCS, and there are
four ports in QSGMII PCS, port 0, 1, 2, 3, all the four ports shared
port 0's MDIO controller, so when programming port 0, we continue to
program other three ports.

Signed-off-by: Shaohui Xie <Shaohui.Xie at freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu at freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong at freescale.com>
---
 drivers/net/fm/eth.c | 22 +++++++++++++++++-----
 1 file changed, 17 insertions(+), 5 deletions(-)

diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index a768a90..12eb9b8 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -41,28 +41,39 @@ static void dtsec_configure_serdes(struct fm_eth *priv)
 	bus.priv = priv->mac->phyregs;
 	bool sgmii_2500 = (priv->enet_if ==
 			PHY_INTERFACE_MODE_SGMII_2500) ? true : false;
+	int i = 0;
+
+qsgmii_loop:
+	if ((priv->enet_if == PHY_INTERFACE_MODE_QSGMII) &&
+	    ((priv->phyaddr % 4) != 0))
+		return;
 
 	/* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
 	value = PHY_SGMII_IF_MODE_SGMII;
 	if (!sgmii_2500)
 		value |= PHY_SGMII_IF_MODE_AN;
 
-	memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x14, value);
+	memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x14, value);
 
 	/* Dev ability according to SGMII specification */
 	value = PHY_SGMII_DEV_ABILITY_SGMII;
-	memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x4, value);
+	memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x4, value);
 
 	/* Adjust link timer for SGMII  -
 	1.6 ms in units of 8 ns = 2 * 10^5 = 0x30d40 */
-	memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x3);
-	memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0xd40);
+	memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x3);
+	memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0xd40);
 
 	/* Restart AN */
 	value = PHY_SGMII_CR_DEF_VAL;
 	if (!sgmii_2500)
 		value |= PHY_SGMII_CR_RESET_AN;
-	memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0, value);
+	memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0, value);
+
+	if ((priv->enet_if == PHY_INTERFACE_MODE_QSGMII) && (i < 3)) {
+		i++;
+		goto qsgmii_loop;
+	}
 #else
 	struct dtsec *regs = priv->mac->base;
 	struct tsec_mii_mng *phyregs = priv->mac->phyregs;
@@ -91,6 +102,7 @@ static void dtsec_init_phy(struct eth_device *dev)
 #endif
 
 	if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII ||
+	    fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII ||
 	    fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
 		dtsec_configure_serdes(fm_eth);
 }
-- 
2.1.0.27.g96db324