[U-Boot] [PATCH 09/14] armv8/ls1043ardb: Add nand boot support

Gong Qianyu Qianyu.Gong at freescale.com
Fri Sep 11 13:07:23 CEST 2015


Signed-off-by: Gong Qianyu <Qianyu.Gong at freescale.com>
Signed-off-by: Hou Zhiqiang <B48286 at freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie at freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu at freescale.com>
---
 arch/arm/Kconfig                                   |  1 +
 arch/arm/cpu/armv8/fsl-lsch2/Makefile              |  1 +
 arch/arm/cpu/armv8/fsl-lsch2/spl.c                 | 91 ++++++++++++++++++++++
 arch/arm/include/asm/arch-fsl-lsch2/config.h       |  2 +
 board/freescale/ls1043ardb/ls1043ardb_pbi.cfg      | 14 ++++
 board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg |  7 ++
 configs/ls1043ardb_nand_defconfig                  |  4 +
 include/configs/ls1043a_common.h                   | 31 ++++++++
 include/configs/ls1043ardb.h                       | 40 ++++++++++
 9 files changed, 191 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f935f19..197c72d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -612,6 +612,7 @@ config TARGET_VEXPRESS64_BASE_FVP
 config TARGET_VEXPRESS64_JUNO
 	bool "Support Versatile Express Juno Development Platform"
 	select ARM64
+	select SUPPORT_SPL
 
 config TARGET_LS2085A_EMU
 	bool "Support ls2085a_emu"
diff --git a/arch/arm/cpu/armv8/fsl-lsch2/Makefile b/arch/arm/cpu/armv8/fsl-lsch2/Makefile
index 23c5bf9..0573659 100644
--- a/arch/arm/cpu/armv8/fsl-lsch2/Makefile
+++ b/arch/arm/cpu/armv8/fsl-lsch2/Makefile
@@ -10,3 +10,4 @@ obj-y += lowlevel.o
 obj-y += speed.o
 obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch2_serdes.o ls1043a_serdes.o
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
+obj-$(CONFIG_SPL) += spl.o
diff --git a/arch/arm/cpu/armv8/fsl-lsch2/spl.c b/arch/arm/cpu/armv8/fsl-lsch2/spl.c
new file mode 100644
index 0000000..980901a
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-lsch2/spl.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <fsl_ifc.h>
+#include <i2c.h>
+#include <asm/arch-fsl-lsch2/immap_lsch2.h>
+#include "../../../../../board/freescale/common/ns_access.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 spl_boot_device(void)
+{
+#ifdef CONFIG_SPL_SPI_SUPPORT
+	return BOOT_DEVICE_SPI;
+#endif
+#ifdef CONFIG_SPL_MMC_SUPPORT
+	return BOOT_DEVICE_MMC1;
+#endif
+#ifdef CONFIG_SPL_NAND_SUPPORT
+	return BOOT_DEVICE_NAND;
+#endif
+	return 0;
+}
+
+u32 spl_boot_mode(void)
+{
+	switch (spl_boot_device()) {
+	case BOOT_DEVICE_MMC1:
+#ifdef CONFIG_SPL_FAT_SUPPORT
+		return MMCSD_MODE_FAT;
+#else
+		return MMCSD_MODE_RAW;
+#endif
+		break;
+	case BOOT_DEVICE_NAND:
+	case BOOT_DEVICE_SPI:
+		return 0;
+		break;
+	default:
+		puts("spl: error: unsupported device\n");
+		hang();
+	}
+}
+
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+#ifdef CONFIG_SPL_NAND_SUPPORT
+	init_early_memctl_regs();
+
+	/*
+	 * There is LS1 SoC issue where NOR, FPGA are inaccessible during
+	 * NAND boot because IFC signals > IFC_AD7 are not enabled.
+	 * This workaround changes RCW source to make all signals enabled.
+	 */
+	u32 porsr1, pinctl;
+	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+	porsr1 = in_be32(&gur->porsr1);
+	pinctl = ((porsr1 & ~(FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK)) | 0x24800000);
+	out_be32((unsigned int *)CONFIG_SYS_DCSR_DCFG_ADDR, pinctl);
+#endif
+
+	/* Set global data pointer */
+	gd = &gdata;
+
+	timer_init();		/* initialize timer */
+
+	get_clocks();
+
+	preloader_console_init();
+
+#ifdef CONFIG_SPL_I2C_SUPPORT
+	i2c_init_all();
+#endif
+	dram_init();
+
+	/* Clear the BSS */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+	enable_layerscape_ns_access();
+#endif
+	board_init_r(NULL, 0);
+}
+#endif
diff --git a/arch/arm/include/asm/arch-fsl-lsch2/config.h b/arch/arm/include/asm/arch-fsl-lsch2/config.h
index 2125161..d0e4ba8 100644
--- a/arch/arm/include/asm/arch-fsl-lsch2/config.h
+++ b/arch/arm/include/asm/arch-fsl-lsch2/config.h
@@ -15,6 +15,8 @@
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
 
 #define CONFIG_SYS_IMMR				0x01000000
+#define CONFIG_SYS_DCSRBAR			0x20000000
+#define CONFIG_SYS_DCSR_DCFG_ADDR	(CONFIG_SYS_DCSRBAR + 0x00220000)
 
 #define CONFIG_SYS_FSL_DDR_ADDR			(CONFIG_SYS_IMMR + 0x00080000)
 #define CONFIG_SYS_CCI400_ADDR			(CONFIG_SYS_IMMR + 0x00180000)
diff --git a/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg b/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
new file mode 100644
index 0000000..f072274
--- /dev/null
+++ b/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
@@ -0,0 +1,14 @@
+#Configure Scratch register
+09570600 00000000
+09570604 10000000
+#Alt base register
+09570158 00001000
+#Disable CCI barrier tranaction
+09570178 0000e010
+09180000 00000008
+#USB PHY frequency sel
+09570418 0000009e
+0957041c 0000009e
+09570420 0000009e
+#flush PBI data
+096100c0 000fffff
diff --git a/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg b/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
new file mode 100644
index 0000000..935ffc0
--- /dev/null
+++ b/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# serdes protocol
+0810000f 0c000000 00000000 00000000
+14550002 80004012 e0106000 61002000
+00000000 00000000 00000000 00038800
+00000000 00001100 00000096 00000001
diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig
new file mode 100644
index 0000000..fffaca0
--- /dev/null
+++ b/configs/ls1043ardb_nand_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT,SYS_FSL_DDR4"
+CONFIG_ARM=y
+CONFIG_TARGET_LS1043ARDB=y
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 139005c..4bda296 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -60,6 +60,37 @@
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
+/* NAND SPL */
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_SPL_PBL_PAD
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_TEXT_BASE		0x10000000
+#define CONFIG_SPL_MAX_SIZE		0x1a000
+#define CONFIG_SPL_STACK		0x1001d000
+#define CONFIG_SPL_PAD_TO		0x1c000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(600 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	CONFIG_SPL_PAD_TO
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_SPL_MALLOC_START	0x80200000
+#define CONFIG_SPL_BSS_START_ADDR	0x80100000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+#define CONFIG_SYS_MONITOR_LEN		0xa0000
+#endif
+
 /* IFC */
 #define CONFIG_FSL_IFC
 /*
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index 1f66201..5e6e09d 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -12,7 +12,11 @@
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
+#if defined(CONFIG_NAND_BOOT)
+#define CONFIG_SYS_TEXT_BASE		0x82000000
+#else
 #define CONFIG_SYS_TEXT_BASE		0x60100000
+#endif
 
 #define CONFIG_SYS_CLK_FREQ		100000000
 #define CONFIG_DDR_CLK_FREQ		100000000
@@ -33,6 +37,14 @@
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
+#endif
+
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
+#endif
+
 /*
  * NOR Flash Definitions
  */
@@ -144,6 +156,25 @@
 #define CONFIG_SYS_CPLD_FTIM3		0x0
 
 /* IFC Timing Params */
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR_CSPR_EXT
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR_CSPR
 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
@@ -161,6 +192,7 @@
 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
 
 #define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_CPLD_CSPR_EXT
 #define CONFIG_SYS_CSPR2		CONFIG_SYS_CPLD_CSPR
@@ -183,9 +215,17 @@
 /*
  * Environment
  */
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_NAND_BOOT)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		(10 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x200000)
 #define CONFIG_ENV_SECT_SIZE		0x20000
 #define CONFIG_ENV_SIZE			0x20000
+#endif
 
 #endif /* __LS1043ARDB_H__ */
-- 
2.1.0.27.g96db324



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