[U-Boot] [PATCH] x86: quark: Configure MTRR to enable cache

[Simon Glass]

On 14 September 2015 at 01:07, Bin Meng <bmeng.cn at gmail.com> wrote:
> Quark SoC does not support MSR MTRRs. Fixed and variable range MTRRs
> are accessed indirectly via the message port and not the traditional
> MSR mechanism. Only UC, WT and WB cache types are supported.
>
> We configure all the fixed range MTRRs with common values (VGA RAM
> as UC, others as WB) and 3 variable range MTRRs for ROM/eSRAM/RAM as
> WB, which significantly improves the boot time performance.
>
> With this commit, it takes only 2 seconds for U-Boot to boot to shell
> on Intel Galileo board. Previously it took about 6 seconds.
>
> Signed-off-by: Bin Meng <bmeng.cn at gmail.com>
> ---
>
>  arch/x86/cpu/quark/dram.c               | 10 ++++++
>  arch/x86/cpu/quark/quark.c              | 57 +++++++++++++++++++++++++++++++++
>  arch/x86/include/asm/arch-quark/quark.h | 44 +++++++++++++++++++++++++
>  3 files changed, 111 insertions(+)

Gosh what a strange an incompatible architecture we have here :-)

Acked-by: Simon Glass <sjg at chromium.org>
Tested-by: Simon Glass <sjg at chromium.org>