[U-Boot] [PATCH 03/19] ARM: k2g: Add pll data
Lokesh Vutla
lokeshvutla at ti.com
Sat Sep 19 12:56:40 CEST 2015
From: Vitaly Andrianov <vitalya at ti.com>
Add pll data for k2g
Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla at ti.com>
---
arch/arm/mach-keystone/clock.c | 5 ++
arch/arm/mach-keystone/include/mach/clock-k2g.h | 18 +++++++
arch/arm/mach-keystone/include/mach/clock.h | 6 +++
arch/arm/mach-keystone/include/mach/hardware.h | 2 +
board/ti/ks2_evm/Makefile | 1 +
board/ti/ks2_evm/board_k2g.c | 63 +++++++++++++++++++++++++
6 files changed, 95 insertions(+)
create mode 100644 arch/arm/mach-keystone/include/mach/clock-k2g.h
create mode 100644 board/ti/ks2_evm/board_k2g.c
diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c
index fc3eadb..31ae936 100644
--- a/arch/arm/mach-keystone/clock.c
+++ b/arch/arm/mach-keystone/clock.c
@@ -31,6 +31,7 @@ const struct keystone_pll_regs keystone_pll_regs[] = {
[TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
[DDR3A_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
[DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
+ [UART_PLL] = {KS2_UARTPLLCTL0, KS2_UARTPLLCTL1},
};
static void wait_for_completion(const struct pll_init_data *data)
@@ -309,6 +310,10 @@ static unsigned long pll_freq_get(int pll)
ret = external_clk[ddr3b_clk];
reg = KS2_DDR3BPLLCTL0;
break;
+ case UART_PLL:
+ ret = external_clk[uart_clk];
+ reg = KS2_UARTPLLCTL0;
+ break;
default:
return 0;
}
diff --git a/arch/arm/mach-keystone/include/mach/clock-k2g.h b/arch/arm/mach-keystone/include/mach/clock-k2g.h
new file mode 100644
index 0000000..4d3f92e
--- /dev/null
+++ b/arch/arm/mach-keystone/include/mach/clock-k2g.h
@@ -0,0 +1,18 @@
+/*
+ * K2G: Clock data
+ *
+ * (C) Copyright 2015
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_CLOCK_K2G_H
+#define __ASM_ARCH_CLOCK_K2G_H
+
+#define PLLSET_CMD_LIST "<pa|arm|ddr3>"
+
+#define DEV_SUPPORTED_SPEEDS 0xfff
+#define ARM_SUPPORTED_SPEEDS 0xfff
+
+#endif
diff --git a/arch/arm/mach-keystone/include/mach/clock.h b/arch/arm/mach-keystone/include/mach/clock.h
index ddc5f8e..0a59fa0 100644
--- a/arch/arm/mach-keystone/include/mach/clock.h
+++ b/arch/arm/mach-keystone/include/mach/clock.h
@@ -24,8 +24,13 @@
#include <asm/arch/clock-k2l.h>
#endif
+#ifdef CONFIG_SOC_K2G
+#include <asm/arch/clock-k2g.h>
+#endif
+
#define CORE_PLL MAIN_PLL
#define DDR3_PLL DDR3A_PLL
+#define NSS_PLL PASS_PLL
#define CLK_LIST(CLK)\
CLK(0, core_pll_clk)\
@@ -75,6 +80,7 @@ enum {
PASS_PLL,
DDR3A_PLL,
DDR3B_PLL,
+ UART_PLL,
MAX_PLL_COUNT,
};
diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h
index cbb836c..2c5167e 100644
--- a/arch/arm/mach-keystone/include/mach/hardware.h
+++ b/arch/arm/mach-keystone/include/mach/hardware.h
@@ -167,6 +167,8 @@ typedef volatile unsigned int *dv_reg_p;
#define KS2_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
#define KS2_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
#define KS2_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374)
+#define KS2_UARTPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x390)
+#define KS2_UARTPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x394)
#define KS2_PLL_CNTRL_BASE 0x02310000
#define KS2_CLOCK_BASE KS2_PLL_CNTRL_BASE
diff --git a/board/ti/ks2_evm/Makefile b/board/ti/ks2_evm/Makefile
index 071dbee..b7c5402 100644
--- a/board/ti/ks2_evm/Makefile
+++ b/board/ti/ks2_evm/Makefile
@@ -13,3 +13,4 @@ obj-$(CONFIG_K2E_EVM) += board_k2e.o
obj-$(CONFIG_K2E_EVM) += ddr3_k2e.o
obj-$(CONFIG_K2L_EVM) += board_k2l.o
obj-$(CONFIG_K2L_EVM) += ddr3_k2l.o
+obj-$(CONFIG_K2G_EVM) += board_k2g.o
diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c
new file mode 100644
index 0000000..6234baa
--- /dev/null
+++ b/board/ti/ks2_evm/board_k2g.c
@@ -0,0 +1,63 @@
+/*
+ * K2G EVM : Board initialization
+ *
+ * (C) Copyright 2015
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <asm/arch/clock.h>
+
+static struct pll_init_data main_pll_config = {MAIN_PLL, 100, 1, 4};
+static struct pll_init_data tetris_pll_config = {TETRIS_PLL, 100, 1, 4};
+static struct pll_init_data uart_pll_config = {UART_PLL, 64, 1, 4};
+static struct pll_init_data nss_pll_config = {NSS_PLL, 250, 3, 2};
+static struct pll_init_data ddr3_pll_config = {DDR3_PLL, 250, 3, 10};
+
+struct pll_init_data *get_pll_init_data(int pll)
+{
+ struct pll_init_data *data = NULL;
+
+ switch (pll) {
+ case MAIN_PLL:
+ data = &main_pll_config;
+ break;
+ case TETRIS_PLL:
+ data = &tetris_pll_config[speed];
+ break;
+ case NSS_PLL:
+ data = &nss_pll_config;
+ break;
+ case UART_PLL:
+ data = &uart_pll_config;
+ break;
+ case DDR3_PLL:
+ data = &ddr_pll_config;
+ break;
+ default:
+ data = NULL;
+ }
+
+ return data;
+}
+
+s16 divn_val[16] = {
+ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
+};
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+ init_plls();
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+void spl_init_keystone_plls(void)
+{
+ init_plls();
+}
+#endif
--
2.1.4
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