[U-Boot] [Patch v2 10/16] ARMv8/ls1043ardb: Add LS1043ARDB board support

Mon Sep 21 19:27:22 CEST 2015

On 09/17/2015 12:06 AM, Gong Qianyu wrote:
> From: Mingkai Hu <Mingkai.Hu at freescale.com>
> 
> LS1043ARDB Specification:
> -------------------------
> Memory subsystem:
>  * 2GByte DDR4 SDRAM (32bit but)

Do you mean "bus" here?

>  * 128 Mbyte NOR flash single-chip memory
>  * 512 Mbyte NAND flash
>  * 16 Mbyte high-speed SPI memory

Do you mean "SPI flash"?

>  * SD connector to interface with the SD memory card
> 
> Ethernet:
>  * XFI 10G port
>  * QSGMII with 4x 1G ports
>  * Two RGMII ports
> 
> PCIe:
>  * PCIe2 (Lanes C) to mini-PCIe slot
>  * PCIe3 (Lanes D) to PCIe slot
> 
> USB 3.0: two super speed USB 3.0 type A ports
> 
> UART: supports two UARTs up to 115200 bps for console
> 
> Signed-off-by: Hou Zhiqiang <B48286 at freescale.com>
> Signed-off-by: Li Yang <leoli at freescale.com>
> Signed-off-by: Mingkai Hu <Mingkai.Hu at freescale.com>
> Signed-off-by: Gong Qianyu <Qianyu.Gong at freescale.com>
> ---
>  V2:
>  Replaced ns_access.h with fsl_csu.h.

<snip>

> --- /dev/null
> +++ b/board/freescale/ls1043ardb/README
> @@ -0,0 +1,87 @@
> +Overview
> +--------
> +The LS1043A Reference Design Board (RDB) is a high-performance computing,
> +evaluation, and development platform that supports the QorIQ LS1043A
> +LayerScape Architecture processor. The LS1043ARDB provides SW development
> +platform for the Freescale LS1043A processor series, with a complete
> +debugging environment. The LS1043A RDB is lead-free and RoHS-compliant.
> +
> +LS1043A SoC Overview
> +--------------------
> +The LS1043A integrated multicore processor combines four ARM Cortex-A53
> +processor cores with datapath acceleration optimized for L2/3 packet
> +processing, single pass security offload and robust traffic management
> +and quality of service.
> +
> +The LS1043A SoC includes the following function and features:
> + - Four 64-bit ARM Cortex-A53 CPUs
> + - 1 MB unified L2 Cache
> + - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
> +   support
> + - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
> +   the following functions:
> +   - Packet parsing, classification, and distribution (FMan)
> +   - Queue management for scheduling, packet sequencing, and congestion
> +     management (QMan)
> +   - Hardware buffer management for buffer allocation and de-allocation (BMan)
> +   - Cryptography acceleration (SEC)
> + - Ethernet interfaces by FMan
> +   - Up to 1 x XFI supporting 10G interface
> +   - Up to 1 x QSGMII
> +   - Up to 4 x SGMII supporting 1000Mbps
> +   - Up to 2 x SGMII supporting 2500Mbps
> +   - Up to 2 x RGMII supporting 1000Mbps
> + - High-speed peripheral interfaces
> +   - Three PCIe 2.0 controllers, one supporting x4 operation
> +   - One serial ATA (SATA 3.0) controllers
> + - Additional peripheral interfaces
> +   - Three high-speed USB 3.0 controllers with integrated PHY
> +   - Enhanced secure digital host controller (eSDXC/eMMC)
> +   - Quad Serial Peripheral Interface (QSPI) Controller
> +   - Serial peripheral interface (SPI) controller
> +   - Four I2C controllers
> +   - Two DUARTs
> +   - Integrated flash controller supporting NAND and NOR flash
> + - QorIQ platform's trust architecture 2.1
> +
> + LS1043ARDB board Overview
> + -----------------------
> + - SERDES Connections, 4 lanes supporting:
> +      - PCI Express 2.0 with two PCIe connectors supporting: miniPCIe card and
> +        standard PCIe card
> +      - QSGMII with x4 RJ45 connector
> +      - XFI with x1 RJ45 connector
> + - DDR Controller
> +     - 2GB 32bits DDR4 SDRAM. Support rates of up to 1600MT/s
> + -IFC/Local Bus
> +    - One 128MB NOR flash 16-bit data bus
> +    - One 512 MB NAND flash with ECC support
> +    - CPLD connection
> + - USB 3.0
> +    - Two super speed USB 3.0 Type A ports
> + - SDHC: connects directly to a full SD/MMC slot
> + - DSPI: 16 MB high-speed flash Memory for boot code and storage (up to 108MHz)
> + - 4 I2C controllers
> + - UART
> +   - Two 4-pin serial ports at up to 115.2 Kbit/s
> +   - Two DB9 D-Type connectors supporting one Serial port each
> + - ARM JTAG support
> +
> +Memory map from core's view
> +----------------------------
> +Start Address	End Address	Description		Size
> +0x00_0000_0000	0x00_000F_FFFF	Secure Boot ROM		1MB
> +0x00_0100_0000	0x00_0FFF_FFFF	CCSRBAR			240MB
> +0x00_1000_0000	0x00_1000_FFFF	OCRAM0			64KB
> +0x00_1001_0000	0x00_1001_FFFF	OCRAM1			64KB
> +0x00_2000_0000	0x00_20FF_FFFF	DCSR			16MB
> +0x00_6000_0000	0x00_67FF_FFFF	IFC - NOR Flash		128MB
> +0x00_7E80_0000	0x00_7E80_FFFF	IFC - NAND Flash	64KB
> +0x00_7FB0_0000	0x00_7FB0_0FFF	IFC - FPGA		4KB
> +0x00_8000_0000	0x00_FFFF_FFFF	DRAM1			2GB
> +
> +Booting Options
> +---------------
> +a) NOR boot
> +b) NAND boot
> +c) SD boot

You don't have NAND or SD boot option with this patch yet. They were added
later. So you can update the README when you have those support.

<snip>
> +
> +#ifdef CONFIG_SYS_DDR_RAW_TIMING

Put a comment with DDR model number here.

> +dimm_params_t ddr_raw_timing = {
> +	.n_ranks = 1,
> +	.rank_density = 2147483648u,
> +	.capacity = 2147483648u,
> +	.primary_sdram_width = 32,
> +	.ec_sdram_width = 0,
> +	.registered_dimm = 0,
> +	.mirrored_dimm = 0,
> +	.n_row_addr = 15,
> +	.n_col_addr = 10,
> +	.bank_addr_bits = 0,
> +	.bank_group_bits = 2,
> +	.edc_config = 0,
> +	.burst_lengths_bitmask = 0x0c,
> +
> +	.tckmin_x_ps = 938,
> +	.tckmax_ps = 1500,
> +	.caslat_x = 0x000DFA00,
> +	.taa_ps = 13500,
> +	.trcd_ps = 13500,
> +	.trp_ps = 13500,
> +	.tras_ps = 33000,
> +	.trc_ps = 46500,
> +	.trfc1_ps = 260000,
> +	.trfc2_ps = 160000,
> +	.trfc4_ps = 110000,
> +	.tfaw_ps = 21000,
> +	.trrds_ps = 3700,
> +	.trrdl_ps = 5300,
> +	.tccdl_ps = 5355,
> +	.refresh_rate_ps = 7800000,
> +	.dq_mapping[0] = 0x0,
> +	.dq_mapping[1] = 0x0,
> +	.dq_mapping[2] = 0x0,
> +	.dq_mapping[3] = 0x0,
> +	.dq_mapping[4] = 0x0,
> +	.dq_mapping[5] = 0x0,
> +	.dq_mapping[6] = 0x0,
> +	.dq_mapping[7] = 0x0,
> +	.dq_mapping[8] = 0x0,
> +	.dq_mapping[9] = 0x0,
> +	.dq_mapping[10] = 0x0,
> +	.dq_mapping[11] = 0x0,
> +	.dq_mapping[12] = 0x0,
> +	.dq_mapping[13] = 0x0,
> +	.dq_mapping[14] = 0x0,
> +	.dq_mapping[15] = 0x0,
> +	.dq_mapping[16] = 0x0,
> +	.dq_mapping[17] = 0x0,
> +	.dq_mapping_ors = 0,
> +};
> +

You may want to try to use -M -C when generating the patch, to see if the patch
can be smaller. I have a feeling many files are copy-n-paste with some modification.

York