[U-Boot] Disabling/Enabling the Data Cache

[Albert ARIBAUD]

Hi Fabio,

Le Tue, 22 Sep 2015 16:01:05 -0300, Fabio Estevam <festevam at gmail.com>
a écrit :

> Hi,
> 
> On a mx6q (armv7) board when I disable and enable the Data Cache the
> following issue is observed:
> 
> => dcache
> Data (writethrough) Cache is ON
> => dcache off
> => dcache on
> data abort
> pc : [<4ff3d340>]          lr : [<4ff3b598>]
> reloc pc : [<17802340>]    lr : [<17800598>]
> sp : 4f538d50  ip : 00000000     fp : 4f841188
> r10: 4ffa4fd4  r9 : 4f538eb0     r8 : 00000002
> r7 : 4f539de8  r6 : 00000000     r5 : 00000000  r4 : 00000000
> r3 : 00a02000  r2 : 32450000     r1 : 4ff94732  r0 : 00000001
> Flags: nZCv  IRQs off  FIQs off  Mode SVC_32
> Resetting CPU ...
> 
> resetting ...
> 
> 
> U-Boot 2015.10-rc3-24232-g324714b-dirty (Sep 22 2015 - 15:08:16 -0300)
> 
> CPU:   Freescale i.MX6DL rev1.1 996 MHz (running at 792 MHz)
> 
> Does anyone have any ideas about this?

No idea with so little context, but the (reloc) pc should indicate where
in the code the abort happened. Maybe that will give us a clue.

> Thanks,
> 
> Fabio Estevam

Cordialement,
Albert ARIBAUD
3ADEV