[U-Boot] [PATCH] sunxi: mmc: Fix clk-delay settings

[Ian Campbell]

On Wed, 2015-09-23 at 21:59 +0200, Hans de Goede wrote:
> In recent allwinner kernel sources the mmc clk-delay settings have been
> slightly tweaked, and for sun9i they are completely different then what
> we are using.
> 
> This commit brings us in sync with what allwinner does, fixing problems
> accessing sdcards on some A33 devices (and likely others).
> 
> For pre sun9i hardware this makes the following changes:
> -At 400Khz change the sample delay from 7 to 0 (first introduced in A31 sdk)

This one applied to sun9i as well as pre I think?

> -At 50 Mhz change the sample delay from 5 to 4 (first introduced in A23 sdk)

By my reading it also changes oclk from 2 to 1 on <sun9i @ >50MHz.

I don't really follow the a/w SDK stuff, is it the case that a given Ann
SDK is tested and supported by Allwinner and used on real devices for
processors Amm < Ann (chronologically, ?

IOW if a change was introduced in the A31 SDK do we then have confidence
that it doesn't break A20 due to Allwinners (and their customer's) use of
the A31 SDK on A20 or are we relying on our own + community testing?

> 
> Signed-off-by: Hans de Goede <hdegoede at redhat.com>
> ---
>  drivers/mmc/sunxi_mmc.c | 16 +++++++++++++---
>  1 file changed, 13 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
> index 25f18ad..e717c44 100644
> --- a/drivers/mmc/sunxi_mmc.c
> +++ b/drivers/mmc/sunxi_mmc.c
> @@ -120,17 +120,27 @@ static int mmc_set_mod_clk(struct sunxi_mmc_host
> *mmchost, unsigned int hz)
>  	/* determine delays */
>  	if (hz <= 400000) {
>  		oclk_dly = 0;
> -		sclk_dly = 7;
> +		sclk_dly = 0;
>  	} else if (hz <= 25000000) {
>  		oclk_dly = 0;
>  		sclk_dly = 5;
> +#ifdef CONFIG_MACH_SUN9I
>  	} else if (hz <= 50000000) {
> -		oclk_dly = 3;
> -		sclk_dly = 5;
> +		oclk_dly = 5;
> +		sclk_dly = 4;
>  	} else {
>  		/* hz > 50000000 */
>  		oclk_dly = 2;
>  		sclk_dly = 4;
> +#else
> +	} else if (hz <= 50000000) {
> +		oclk_dly = 3;
> +		sclk_dly = 4;
> +	} else {
> +		/* hz > 50000000 */
> +		oclk_dly = 1;
> +		sclk_dly = 4;
> +#endif
>  	}
>  
>  	writel(CCM_MMC_CTRL_ENABLE | pll |
> CCM_MMC_CTRL_SCLK_DLY(sclk_dly) |