[U-Boot] Unaligned flush_dcache_range in axs101.c

[Alexander Graf]

Hi Alexey,

Marek just pointed out to me the fact that flush_dcache_range on arm
expects cache line aligned arguments. However, it seems like in axs101.c
we have an unaligned cache flush:

  flush_dcache_range(RESET_VECTOR_ADDR, RESET_VECTOR_ADDR + sizeof(int));

Could you please verify whether this is correct and if not just send a
quick patch to fix it?


Thanks!

Alex