[U-Boot] FPGA detection failure on Cyclone V soc development kit

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Marek Vasut <marex at denx.de> writes:

> On 04/06/2016 05:29 PM, Dinh Nguyen wrote:
>> On Wed, Apr 6, 2016 at 10:07 AM, Marek Vasut <marek.vasut at gmail.com> wrote:
>>>
>>> I pushed some DDR fixes into u-boot-socfpga/ddr branch [1], which fixed
>>> DDR calibration issue on a board I have in here. Can you try them ? Thanks
>>>
>>> [1]
>>> http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=shortlog;h=refs/heads/ddr
>>>
>> 
>> I'll do it first thing when I get back from ELC.
>
> Cool. I will do proper submission by then. I think Mans had a CV SoCDK
> which didn't boot with the mainline SPL, so it'd be cool if he could try.

I will when I get back from ELC.

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