[U-Boot] [RFC PATCH] powerpc: Disable flush or invalidate dcache by range for some SoCs

[York Sun]

Commit ac337168a unified functions to flush and invalidate dcache by
range. These two functions were no-op for SoCs other than 4xx and
MPC86xx. Adding these functions seemed to be correct but introduced
issues when the dcache is flushed. While the root cause is under
investigation, disable these functions for affected SoCs so various
drivers can work.

Signed-off-by: York Sun <york.sun at nxp.com>

---

 arch/powerpc/lib/ppccache.S |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/powerpc/lib/ppccache.S b/arch/powerpc/lib/ppccache.S
index b96dbc6..66cf02d 100644
--- a/arch/powerpc/lib/ppccache.S
+++ b/arch/powerpc/lib/ppccache.S
@@ -65,6 +65,7 @@ ppcSync:
  * flush_dcache_range(unsigned long start, unsigned long stop)
  */
 _GLOBAL(flush_dcache_range)
+#if defined(CONFIG_4xx) || defined(CONFIG_MPC86xx)
 	li	r5,L1_CACHE_BYTES-1
 	andc	r3,r3,r5
 	subf	r4,r3,r4
@@ -77,6 +78,7 @@ _GLOBAL(flush_dcache_range)
 	addi	r3,r3,L1_CACHE_BYTES
 	bdnz	1b
 	sync				/* wait for dcbst's to get to ram */
+#endif
 	blr
 
 /*
@@ -87,6 +89,7 @@ _GLOBAL(flush_dcache_range)
  * invalidate_dcache_range(unsigned long start, unsigned long stop)
  */
 _GLOBAL(invalidate_dcache_range)
+#if defined(CONFIG_4xx) || defined(CONFIG_MPC86xx)
 	li	r5,L1_CACHE_BYTES-1
 	andc	r3,r3,r5
 	subf	r4,r3,r4
@@ -100,5 +103,6 @@ _GLOBAL(invalidate_dcache_range)
 	addi	r3,r3,L1_CACHE_BYTES
 	bdnz	1b
 	sync				/* wait for dcbi's to get to ram */
+#endif
 	blr
 
-- 
1.7.9.5