[U-Boot] [PATCH] armv8/ls2080a: configure PMU's PCTBENR to enable WDT

[Yunhui Cui]

From: Yunhui Cui <yunhui.cui at nxp.com>

The SP805-WDT module on LS2080A and LS2085A, requires configuration
of PMU's PCTBENR register to enable watchdog counter decrement and
reset signal generation. In order not to affect the sp805wdt driver
frame, we enable the watchdog clk in advance.

Signed-off-by: Yunhui Cui <yunhui.cui at nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c        | 18 ++++++++++++++++++
 arch/arm/include/asm/arch-fsl-layerscape/soc.h |  1 +
 board/freescale/ls2080aqds/ls2080aqds.c        |  2 ++
 board/freescale/ls2080ardb/ls2080ardb.c        |  2 ++
 4 files changed, 23 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index a76447e..06c950f 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -17,6 +17,24 @@
 #endif
 
 DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+/*
+ * Set the bit corresponding to our watchDog-id in the
+ * PMU-Physical Core Time Base Enable Register (PCTBENR)
+ * to allow the WDT counter to decrement and raise a reset
+ * request (if configured in the WDTCONTROL register).
+ */
+void enable_watchdog_clk(void)
+{
+	#define FSL_PMU_REG_BASE	0x1E30000
+	#define FSL_PMU_PCTBENR_OFFSET	0x8A0
+	u32 pmu_val;
+
+	pmu_val = *(u32 *)(FSL_PMU_REG_BASE + FSL_PMU_PCTBENR_OFFSET);
+	*(u32 *)(FSL_PMU_REG_BASE + FSL_PMU_PCTBENR_OFFSET) = pmu_val | 0xff;
+}
+#endif
+
 
 #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
 /*
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 56989e1..32c9185 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -91,6 +91,7 @@ void fsl_lsch2_early_init_f(void);
 #endif
 
 void cpu_name(char *name);
+void enable_watchdog_clk(void);
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
 void erratum_a009635(void);
 #endif
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c
index e1a521d..8ebc96a 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -213,6 +213,8 @@ int board_init(void)
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 	rtc_enable_32khz_output();
 
+	enable_watchdog_clk();
+
 	return 0;
 }
 
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index 8201048..ad8324a 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -181,6 +181,8 @@ int board_init(void)
 	/* invert AQR405 IRQ pins polarity */
 	out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
 
+	enable_watchdog_clk();
+
 	return 0;
 }
 
-- 
2.1.0.27.g96db324