[U-Boot] [PATCH 01/10] ddr: altera: Replace ad-hoc constant with macro

[George Broz]

On 6 April 2016 at 19:03, Marek Vasut <marex at denx.de> wrote:
> The bit 22 is in fact DQS tracking enable bit (dqstrken) and there
> is a macro for this bit already, so use it.
>
> Signed-off-by: Marek Vasut <marex at denx.de>
> Cc: Dinh Nguyen <dinguyen at opensource.altera.com>
> Cc: Chin Liang See <clsee at altera.com>
> ---
>  drivers/ddr/altera/sequencer.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
> index 79c265f..34b1aa7 100644
> --- a/drivers/ddr/altera/sequencer.c
> +++ b/drivers/ddr/altera/sequencer.c
> @@ -3486,7 +3486,7 @@ static int run_mem_calibrate(void)
>         writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
>
>         /* Stop tracking manager. */
> -       clrbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
> +       clrbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK);
>
>         phy_mgr_initialize();
>         rw_mgr_mem_initialize();
> @@ -3507,7 +3507,7 @@ static int run_mem_calibrate(void)
>         writel(0x2, &phy_mgr_cfg->mux_sel);
>
>         /* Start tracking manager. */
> -       setbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
> +       setbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK);
>
>         return pass;
>  }
> --
> 2.7.0
>

Tested on: SoCKit, DE0_Nano_SoC
Tested-by: George Broz <brozgeo at gmail.com>