[U-Boot] [PATCH] Revert "T2080QDS/PCIe: Soft Reset PCIe on T2080QDS for down-training issue"

Zhao Qiang qiang.zhao at nxp.com
Mon Apr 11 10:53:18 CEST 2016


This reverts commit 5066e62847bddf6030262ade2aa3e7bcdc930037.

The reverted patch will block t2080RDB iNiC, it was a workaround for
T2080QDS
down-training issue, we need to revert it and find the root cause for
T2080QDS
down-training issue.

Signed-off-by: Zhao Qiang <qiang.zhao at nxp.com>
---
 drivers/pci/fsl_pci_init.c | 15 ---------------
 include/configs/T208xQDS.h |  1 -
 2 files changed, 16 deletions(-)

diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 52792dc..1143178 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -444,21 +444,6 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
 			ltssm = (in_be32(&pci->pex_csr0)
 				& PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
 			enabled = (ltssm == 0x11) ? 1 : 0;
-#ifdef CONFIG_FSL_PCIE_RESET
-			int i;
-			/* assert PCIe reset */
-			setbits_be32(&pci->pdb_stat, 0x08000000);
-			(void) in_be32(&pci->pdb_stat);
-			udelay(1000);
-			/* clear PCIe reset */
-			clrbits_be32(&pci->pdb_stat, 0x08000000);
-			asm("sync;isync");
-			for (i = 0; i < 100 && ltssm < PCI_LTSSM_L0; i++) {
-				pci_hose_read_config_word(hose, dev, PCI_LTSSM,
-							  &ltssm);
-				udelay(1000);
-			}
-#endif
 		} else {
 		/* pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm); */
 		/* enabled = ltssm >= PCI_LTSSM_L0; */
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 5957fa8..c895818 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -559,7 +559,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_PCIE2		/* PCIE controler 2 */
 #define CONFIG_PCIE3		/* PCIE controler 3 */
 #define CONFIG_PCIE4		/* PCIE controler 4 */
-#define CONFIG_FSL_PCIE_RESET
 #define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
-- 
2.1.0.27.g96db324



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