[U-Boot] [PATCH 38/60] ARM: tegra: remove tegra_get_chip()
Stephen Warren
swarren at wwwdotorg.org
Tue Apr 19 22:59:18 CEST 2016
From: Stephen Warren <swarren at nvidia.com>
U-Boot is compiled for a single board, which in turn uses a specific SoC.
There's no need to make runtime decisions based on SoC ID. While there's
certainly an argument for making the code support different SoCs at
run-time, the Tegra code is so far from that possible ideal that the
existing runtime code is an anomaly. If this changes in the future, all
runtime decisions should likely be based on DT anyway.
Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
arch/arm/mach-tegra/ap.c | 106 ++++++++++-----------------------
arch/arm/mach-tegra/cache.c | 20 +++----
arch/arm/mach-tegra/cpu.c | 16 ++---
arch/arm/mach-tegra/cpu.h | 6 --
arch/arm/mach-tegra/tegra20/warmboot.c | 20 ++-----
5 files changed, 51 insertions(+), 117 deletions(-)
diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c
index a200010e2937..a8e3e8b7dfcb 100644
--- a/arch/arm/mach-tegra/ap.c
+++ b/arch/arm/mach-tegra/ap.c
@@ -10,7 +10,6 @@
#include <common.h>
#include <linux/bug.h>
#include <asm/io.h>
-#include <asm/arch/gp_padctrl.h>
#include <asm/arch-tegra/clock.h>
#include <asm/arch-tegra/tegra.h>
#include <soc/mc.h>
@@ -19,23 +18,6 @@
#include "pmc.h"
#include "scu.h"
-int tegra_get_chip(void)
-{
- int rev;
- struct apb_misc_gp_ctlr *gp =
- (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
-
- /*
- * This is undocumented, Chip ID is bits 15:8 of the register
- * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
- * Tegra30, 0x35 for T114, and 0x40 for Tegra124.
- */
- rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
- debug("%s: CHIPID is 0x%02X\n", __func__, rev);
-
- return rev;
-}
-
int tegra_get_sku_info(void)
{
int sku_id;
@@ -49,74 +31,47 @@ int tegra_get_sku_info(void)
int tegra_get_chip_sku(void)
{
- uint sku_id, chip_id;
+#ifdef CONFIG_TEGRA20
+ uint sku_id;
- chip_id = tegra_get_chip();
sku_id = tegra_get_sku_info();
-
- switch (chip_id) {
- case CHIPID_TEGRA20:
- switch (sku_id) {
- case SKU_ID_T20_7:
- case SKU_ID_T20:
- return TEGRA_SOC_T20;
- case SKU_ID_T25SE:
- case SKU_ID_AP25:
- case SKU_ID_T25:
- case SKU_ID_AP25E:
- case SKU_ID_T25E:
- return TEGRA_SOC_T25;
- }
- break;
- case CHIPID_TEGRA30:
- switch (sku_id) {
- case SKU_ID_T33:
- case SKU_ID_T30:
- case SKU_ID_TM30MQS_P_A3:
- default:
- return TEGRA_SOC_T30;
- }
- break;
- case CHIPID_TEGRA114:
- switch (sku_id) {
- case SKU_ID_T114_ENG:
- case SKU_ID_T114_1:
- default:
- return TEGRA_SOC_T114;
- }
- break;
- case CHIPID_TEGRA124:
- switch (sku_id) {
- case SKU_ID_T124_ENG:
- default:
- return TEGRA_SOC_T124;
- }
- break;
- case CHIPID_TEGRA210:
- switch (sku_id) {
- case SKU_ID_T210_ENG:
- default:
- return TEGRA_SOC_T210;
- }
- break;
+ switch (sku_id) {
+ case SKU_ID_T20_7:
+ case SKU_ID_T20:
+ return TEGRA_SOC_T20;
+ case SKU_ID_T25SE:
+ case SKU_ID_AP25:
+ case SKU_ID_T25:
+ case SKU_ID_AP25E:
+ case SKU_ID_T25E:
+ return TEGRA_SOC_T25;
+ default:
+ /* unknown chip/sku id */
+ printf("ERROR: UNKNOWN SKU ID 0x%02X\n", sku_id);
+ return TEGRA_SOC_UNKNOWN;
}
-
- /* unknown chip/sku id */
- printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n",
- __func__, chip_id, sku_id);
- return TEGRA_SOC_UNKNOWN;
+#endif
+#ifdef CONFIG_TEGRA30
+ return TEGRA_SOC_T30;
+#endif
+#ifdef CONFIG_TEGRA114
+ return TEGRA_SOC_T114;
+#endif
+#ifdef CONFIG_TEGRA124
+ return TEGRA_SOC_T124;
+#endif
+#ifdef CONFIG_TEGRA210
+ return TEGRA_SOC_T210;
+#endif
}
#ifndef CONFIG_ARM64
static void enable_scu(void)
{
+#ifdef CONFIG_TEGRA20
struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE;
u32 reg;
- /* Only enable the SCU on T20/T25 */
- if (tegra_get_chip() != CHIPID_TEGRA20)
- return;
-
/* If SCU already setup/enabled, return */
if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE)
return;
@@ -128,6 +83,7 @@ static void enable_scu(void)
reg = readl(&scu->scu_ctrl);
reg |= SCU_CTRL_ENABLE;
writel(reg, &scu->scu_ctrl);
+#endif
}
static u32 get_odmdata(void)
diff --git a/arch/arm/mach-tegra/cache.c b/arch/arm/mach-tegra/cache.c
index b93814fcb96b..a41a7b9e2868 100644
--- a/arch/arm/mach-tegra/cache.c
+++ b/arch/arm/mach-tegra/cache.c
@@ -8,31 +8,29 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/gp_padctrl.h>
#include "cpu.h"
#ifndef CONFIG_ARM64
void config_cache(void)
{
- u32 reg = 0;
-
/* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */
asm volatile(
"mrc p15, 0, r0, c1, c0, 1\n"
"orr r0, r0, #0x41\n"
"mcr p15, 0, r0, c1, c0, 1\n");
- /* Currently, only Tegra114+ needs this L2 cache change to boot Linux */
- if (tegra_get_chip() < CHIPID_TEGRA114)
- return;
-
+#if defined(CONFIG_TEGRA114) || defined(CONFIG_TEGRA124)
/*
* Systems with an architectural L2 cache must not use the PL310.
* Config L2CTLR here for a data RAM latency of 3 cycles.
*/
- asm("mrc p15, 1, %0, c9, c0, 2" : : "r" (reg));
- reg &= ~7;
- reg |= 2;
- asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg));
+ {
+ u32 reg;
+ asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (reg));
+ reg &= ~7;
+ reg |= 2;
+ asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg));
+ }
+#endif
}
#endif
diff --git a/arch/arm/mach-tegra/cpu.c b/arch/arm/mach-tegra/cpu.c
index 3562a2d2188a..cc60908677a1 100644
--- a/arch/arm/mach-tegra/cpu.c
+++ b/arch/arm/mach-tegra/cpu.c
@@ -172,7 +172,6 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
u32 divp, u32 cpcon)
{
struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU];
- int chip = tegra_get_chip();
u32 reg;
debug("%s entry\n", __func__);
@@ -189,11 +188,12 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
reg |= (divn << pllinfo->n_shift) | (divp << pllinfo->p_shift);
writel(reg, &pll->pll_base);
+ reg = 0;
+
+#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30)
/* Set cpcon to PLLX_MISC */
- if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30)
- reg = (cpcon << pllinfo->kcp_shift);
- else
- reg = 0;
+ reg |= (cpcon << pllinfo->kcp_shift);
+#endif
/*
* TODO(twarren at nvidia.com) Check which SoCs use DCCON
@@ -230,15 +230,11 @@ void init_pllx(void)
{
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX];
- int soc_type, sku_info, chip_sku;
+ int sku_info, chip_sku;
enum clock_osc_freq osc;
struct clk_pll_table *sel;
debug("%s entry\n", __func__);
- /* get SOC (chip) type */
- soc_type = tegra_get_chip();
- debug("%s: SoC = 0x%02X\n", __func__, soc_type);
-
/* get SKU info */
sku_info = tegra_get_sku_info();
debug("%s: SKU info byte = 0x%02X\n", __func__, sku_info);
diff --git a/arch/arm/mach-tegra/cpu.h b/arch/arm/mach-tegra/cpu.h
index f1f5b179c198..ee4f7868baf7 100644
--- a/arch/arm/mach-tegra/cpu.h
+++ b/arch/arm/mach-tegra/cpu.h
@@ -64,12 +64,6 @@ void powerup_cpu(void);
void reset_A9_cpu(int reset);
void start_cpu(u32 reset_vector);
/**
- * Returns the pure SOC (chip ID) from the HIDREV register
- *
- * @return SOC ID - see CHIPID_TEGRAxx...
- */
-int tegra_get_chip(void);
-/**
* Returns the SKU ID from the sku_info register
*
* @return SKU ID - see SKU_ID_Txx...
diff --git a/arch/arm/mach-tegra/tegra20/warmboot.c b/arch/arm/mach-tegra/tegra20/warmboot.c
index 9d67bdef494a..1159f05a5dc3 100644
--- a/arch/arm/mach-tegra/tegra20/warmboot.c
+++ b/arch/arm/mach-tegra/tegra20/warmboot.c
@@ -242,22 +242,12 @@ static int ap20_is_production_mode(void)
static enum fuse_operating_mode fuse_get_operation_mode(void)
{
- u32 chip_id;
- struct apb_misc_gp_ctlr *gp =
- (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
-
- chip_id = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >>
- HIDREV_CHIPID_SHIFT;
- if (chip_id == CHIPID_TEGRA20) {
- if (ap20_is_odm_production_mode()) {
- printf("!! odm_production_mode is not supported !!\n");
- return MODE_UNDEFINED;
- } else
- if (ap20_is_production_mode())
- return MODE_PRODUCTION;
- else
- return MODE_UNDEFINED;
+ if (ap20_is_odm_production_mode()) {
+ printf("!! odm_production_mode is not supported !!\n");
+ return MODE_UNDEFINED;
}
+ if (ap20_is_production_mode())
+ return MODE_PRODUCTION;
return MODE_UNDEFINED;
}
--
2.8.1
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