[U-Boot] [PATCH] mx6ul_evk: Remove SPL support
Dennis Gilmore
dennis at ausil.us
Thu Apr 21 17:11:12 CEST 2016
On Tuesday, April 19, 2016 10:11:37 PM CDT Stefano Babic wrote:
> Hi Fabio,
>
> On 19/04/2016 17:19, Fabio Estevam wrote:
> > Currently mx6ul evk fails to boot with some SD cards such as
> > SanDisk microSD HC - 8GB:
> >
> > U-Boot SPL 2016.05-rc1-28384-g108f841 (Apr 19 2016 - 11:19:11)
> > Trying to boot from MMC1
> > spl: mmc block read error
> > SPL: failed to boot from all boot devices
> > ### ERROR ### Please RESET the board ###
>
> Well, it does not work because mmc is not working - mmc should be fixed,
> then.
>
> > As a proper fix for SPL is not available, change to booting via
> > non-SPL mode, so that we can have always have a reliable boot.
> >
> > Signed-off-by: Fabio Estevam <fabio.estevam at nxp.com>
> > ---
> >
> > board/freescale/mx6ul_14x14_evk/imximage.cfg | 88 +++++++++++
> > board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 172
> > ---------------------- configs/mx6ul_14x14_evk_defconfig
> > | 3 +-
> > 3 files changed, 89 insertions(+), 174 deletions(-)
> > create mode 100644 board/freescale/mx6ul_14x14_evk/imximage.cfg
> >
> > diff --git a/board/freescale/mx6ul_14x14_evk/imximage.cfg
> > b/board/freescale/mx6ul_14x14_evk/imximage.cfg new file mode 100644
> > index 0000000..f413753
> > --- /dev/null
> > +++ b/board/freescale/mx6ul_14x14_evk/imximage.cfg
> > @@ -0,0 +1,88 @@
> > +/*
> > + * Copyright (C) 2015 Freescale Semiconductor, Inc.
> > + *
> > + * SPDX-License-Identifier: GPL-2.0+
> > + *
> > + * Refer docs/README.imxmage for more details about how-to configure
> > + * and create imximage boot image
> > + *
> > + * The syntax is taken as close as possible with the kwbimage
> > + */
> > +
> > +#define __ASSEMBLY__
> > +#include <config.h>
> > +
> > +/* image version */
> > +
> > +IMAGE_VERSION 2
> > +
> > +/*
> > + * Boot Device : one of
> > + * spi/sd/nand/onenand, qspi/nor
> > + */
> > +BOOT_FROM sd
> > +
> > +/* New DDR type MT41K256M16TW-107 */
> > +
> > +/* Enable all clocks */
> > +DATA 4 0x020c4068 0xffffffff
> > +DATA 4 0x020c406c 0xffffffff
> > +DATA 4 0x020c4070 0xffffffff
> > +DATA 4 0x020c4074 0xffffffff
> > +DATA 4 0x020c4078 0xffffffff
> > +DATA 4 0x020c407c 0xffffffff
> > +DATA 4 0x020c4080 0xffffffff
> > +
> > +DATA 4 0x020E04B4 0x000C0000
> > +DATA 4 0x020E04AC 0x00000000
> > +DATA 4 0x020E027C 0x00000030
> > +DATA 4 0x020E0250 0x00000030
> > +DATA 4 0x020E024C 0x00000030
> > +DATA 4 0x020E0490 0x00000030
> > +DATA 4 0x020E0288 0x00000030
> > +DATA 4 0x020E0270 0x00000000
> > +DATA 4 0x020E0260 0x00000030
> > +DATA 4 0x020E0264 0x00000030
> > +DATA 4 0x020E04A0 0x00000030
> > +DATA 4 0x020E0494 0x00020000
> > +DATA 4 0x020E0280 0x00000030
> > +DATA 4 0x020E0284 0x00000030
> > +DATA 4 0x020E04B0 0x00020000
> > +DATA 4 0x020E0498 0x00000030
> > +DATA 4 0x020E04A4 0x00000030
> > +DATA 4 0x020E0244 0x00000030
> > +DATA 4 0x020E0248 0x00000030
> > +DATA 4 0x021B001C 0x00008000
> > +DATA 4 0x021B0800 0xA1390003
> > +DATA 4 0x021B080C 0x00000000
> > +DATA 4 0x021B083C 0x41570155
> > +DATA 4 0x021B0848 0x4040474A
> > +DATA 4 0x021B0850 0x40405550
> > +DATA 4 0x021B081C 0x33333333
> > +DATA 4 0x021B0820 0x33333333
> > +DATA 4 0x021B082C 0xf3333333
> > +DATA 4 0x021B0830 0xf3333333
> > +DATA 4 0x021B08C0 0x00921012
> > +DATA 4 0x021B08b8 0x00000800
> > +DATA 4 0x021B0004 0x0002002D
> > +DATA 4 0x021B0008 0x1B333030
> > +DATA 4 0x021B000C 0x676B52F3
> > +DATA 4 0x021B0010 0xB66D0B63
> > +DATA 4 0x021B0014 0x01FF00DB
> > +DATA 4 0x021B0018 0x00201740
> > +DATA 4 0x021B001C 0x00008000
> > +DATA 4 0x021B002C 0x000026D2
> > +DATA 4 0x021B0030 0x006B1023
> > +DATA 4 0x021B0040 0x0000004F
> > +DATA 4 0x021B0000 0x84180000
> > +DATA 4 0x021B0890 0x23400A38
> > +DATA 4 0x021B001C 0x02008032
> > +DATA 4 0x021B001C 0x00008033
> > +DATA 4 0x021B001C 0x00048031
> > +DATA 4 0x021B001C 0x15208030
> > +DATA 4 0x021B001C 0x04008040
> > +DATA 4 0x021B0020 0x00000800
> > +DATA 4 0x021B0818 0x00000227
> > +DATA 4 0x021B0004 0x0002552D
> > +DATA 4 0x021B0404 0x00011006
> > +DATA 4 0x021B001C 0x00000000
> > diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
> > b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c index
> > 88d3fbd..4de5ece 100644
> > --- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
> > +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
> > @@ -703,175 +703,3 @@ int checkboard(void)
> >
> > return 0;
> >
> > }
> >
> > -
> > -#ifdef CONFIG_SPL_BUILD
> > -#include <libfdt.h>
> > -#include <spl.h>
> > -#include <asm/arch/mx6-ddr.h>
> > -
> > -
> > -static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
> > - .grp_addds = 0x00000030,
> > - .grp_ddrmode_ctl = 0x00020000,
> > - .grp_b0ds = 0x00000030,
> > - .grp_ctlds = 0x00000030,
> > - .grp_b1ds = 0x00000030,
> > - .grp_ddrpke = 0x00000000,
> > - .grp_ddrmode = 0x00020000,
> > -#ifdef CONFIG_TARGET_MX6UL_9X9_EVK
> > - .grp_ddr_type = 0x00080000,
> > -#else
> > - .grp_ddr_type = 0x000c0000,
> > -#endif
> > -};
> > -
> > -#ifdef CONFIG_TARGET_MX6UL_9X9_EVK
> > -static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
> > - .dram_dqm0 = 0x00000030,
> > - .dram_dqm1 = 0x00000030,
> > - .dram_ras = 0x00000030,
> > - .dram_cas = 0x00000030,
> > - .dram_odt0 = 0x00000000,
> > - .dram_odt1 = 0x00000000,
> > - .dram_sdba2 = 0x00000000,
> > - .dram_sdclk_0 = 0x00000030,
> > - .dram_sdqs0 = 0x00003030,
> > - .dram_sdqs1 = 0x00003030,
> > - .dram_reset = 0x00000030,
> > -};
> > -
> > -static struct mx6_mmdc_calibration mx6_mmcd_calib = {
> > - .p0_mpwldectrl0 = 0x00000000,
> > - .p0_mpdgctrl0 = 0x20000000,
> > - .p0_mprddlctl = 0x4040484f,
> > - .p0_mpwrdlctl = 0x40405247,
> > - .mpzqlp2ctl = 0x1b4700c7,
> > -};
> > -
> > -static struct mx6_lpddr2_cfg mem_ddr = {
> > - .mem_speed = 800,
> > - .density = 2,
> > - .width = 16,
> > - .banks = 4,
> > - .rowaddr = 14,
> > - .coladdr = 10,
> > - .trcd_lp = 1500,
> > - .trppb_lp = 1500,
> > - .trpab_lp = 2000,
> > - .trasmin = 4250,
> > -};
> > -
> > -struct mx6_ddr_sysinfo ddr_sysinfo = {
> > - .dsize = 0,
> > - .cs_density = 18,
> > - .ncs = 1,
> > - .cs1_mirror = 0,
> > - .walat = 0,
> > - .ralat = 5,
> > - .mif3_mode = 3,
> > - .bi_on = 1,
> > - .rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */
> > - .rtt_nom = 0,
> > - .sde_to_rst = 0, /* LPDDR2 does not need this field */
> > - .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
> > - .ddr_type = DDR_TYPE_LPDDR2,
> > -};
> > -
> > -#else
> > -static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
> > - .dram_dqm0 = 0x00000030,
> > - .dram_dqm1 = 0x00000030,
> > - .dram_ras = 0x00000030,
> > - .dram_cas = 0x00000030,
> > - .dram_odt0 = 0x00000030,
> > - .dram_odt1 = 0x00000030,
> > - .dram_sdba2 = 0x00000000,
> > - .dram_sdclk_0 = 0x00000008,
> > - .dram_sdqs0 = 0x00000038,
> > - .dram_sdqs1 = 0x00000030,
> > - .dram_reset = 0x00000030,
> > -};
> > -
> > -static struct mx6_mmdc_calibration mx6_mmcd_calib = {
> > - .p0_mpwldectrl0 = 0x00070007,
> > - .p0_mpdgctrl0 = 0x41490145,
> > - .p0_mprddlctl = 0x40404546,
> > - .p0_mpwrdlctl = 0x4040524D,
> > -};
> > -
> > -struct mx6_ddr_sysinfo ddr_sysinfo = {
> > - .dsize = 0,
> > - .cs_density = 20,
> > - .ncs = 1,
> > - .cs1_mirror = 0,
> > - .rtt_wr = 2,
> > - .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
> > - .walat = 1, /* Write additional latency */
> > - .ralat = 5, /* Read additional latency */
> > - .mif3_mode = 3, /* Command prediction working mode */
> > - .bi_on = 1, /* Bank interleaving enabled */
> > - .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
> > - .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
> > - .ddr_type = DDR_TYPE_DDR3,
> > -};
> > -
> > -static struct mx6_ddr3_cfg mem_ddr = {
> > - .mem_speed = 800,
> > - .density = 4,
> > - .width = 16,
> > - .banks = 8,
> > - .rowaddr = 15,
> > - .coladdr = 10,
> > - .pagesz = 2,
> > - .trcd = 1375,
> > - .trcmin = 4875,
> > - .trasmin = 3500,
> > -};
> > -#endif
> > -
> > -static void ccgr_init(void)
> > -{
> > - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> > -
> > - writel(0xFFFFFFFF, &ccm->CCGR0);
> > - writel(0xFFFFFFFF, &ccm->CCGR1);
> > - writel(0xFFFFFFFF, &ccm->CCGR2);
> > - writel(0xFFFFFFFF, &ccm->CCGR3);
> > - writel(0xFFFFFFFF, &ccm->CCGR4);
> > - writel(0xFFFFFFFF, &ccm->CCGR5);
> > - writel(0xFFFFFFFF, &ccm->CCGR6);
> > - writel(0xFFFFFFFF, &ccm->CCGR7);
> > -}
> > -
> > -static void spl_dram_init(void)
> > -{
> > - mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
> > - mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
> > -}
> > -
> > -void board_init_f(ulong dummy)
> > -{
> > - /* setup AIPS and disable watchdog */
> > - arch_cpu_init();
> > -
> > - ccgr_init();
> > -
> > - /* iomux and setup of i2c */
> > - board_early_init_f();
> > -
> > - /* setup GP timer */
> > - timer_init();
> > -
> > - /* UART clocks enabled and gd valid - init serial console */
> > - preloader_console_init();
> > -
> > - /* DDR initialization */
> > - spl_dram_init();
> > -
> > - /* Clear the BSS. */
> > - memset(__bss_start, 0, __bss_end - __bss_start);
> > -
> > - /* load/boot image from boot device */
> > - board_init_r(NULL, 0);
> > -}
> > -#endif
> > diff --git a/configs/mx6ul_14x14_evk_defconfig
> > b/configs/mx6ul_14x14_evk_defconfig index 77d78e7..cdd8446 100644
> > --- a/configs/mx6ul_14x14_evk_defconfig
> > +++ b/configs/mx6ul_14x14_evk_defconfig
> > @@ -1,8 +1,7 @@
> >
> > CONFIG_ARM=y
> > CONFIG_ARCH_MX6=y
> > CONFIG_TARGET_MX6UL_14X14_EVK=y
> >
> > -CONFIG_SPL=y
> > -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
> > +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_evk/imxi
> > mage.cfg">
> > CONFIG_CMD_GPIO=y
> > CONFIG_CMD_DHCP=y
> > CONFIG_CMD_PING=y
>
> I disagree on this - SPL should be fixed, not removed.
>
> Best regards,
> Stefano Babic
ack, I agree that SPL should be fixed
Dennis
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