[U-Boot] [PATCH] sunxi: mctl_mem_matches: Add missing memory barrier

[Ian Campbell]

On Fri, 2016-04-15 at 09:34 +0200, Hans de Goede wrote:
> > I wonder if what you are observing could be possibly explained by just
> > a usual data corruption problem? Which may be happening when the DRAM
> > clock speed is set higher than this particular device is able to handle
> > in a reliable way. Inserting just one or more NOP instructions instead
> > of the barrier could possibly change some timings too.
> > 
> > If this patch helps, then it's fine. But I wonder if it is not merely
> > making the problem latent instead of fixing the root cause?
> I do believe that this patch addresses a real problem and is not hiding
> some dram timing issues, I might be wrong about the write-buffer being
> the cause, it could simply be that the compiler is doing something bad
> (despite the accesses being marked as volatile)  and that the DSB stops
> the compiler from optimizing things too much.

I have a _very_ vague memory of seeing something not disimilar to this
(apparent write buffer interactions with MMU disabled) in the early
days of Xen development, but that was probably on models and so may not
have been representative of the intended behaviour of eventual silicon.

It might be interesting to have a look at the generated assembly and
see if it differs in more or less than the addition of the single
instruction and perhaps experiment with just a compiler barrier.

Andre, do you have any insights on this?

Ian.