[U-Boot] [PATCH 5/5] arm: Show cache warnings in U-Boot proper only

[Michal Simek]

Hi,

On 2.8.2016 08:42, Hannes Schmelzer wrote:
> On 20.06.2016 03:43, Simon Glass wrote:
>> Avoid bloating the SPL image size.
>>
>> Signed-off-by: Simon Glass <sjg at chromium.org>
>> ---
>>
>>   arch/arm/lib/cache.c | 4 ++--
>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
>> index 642a952..d330b09 100644
>> --- a/arch/arm/lib/cache.c
>> +++ b/arch/arm/lib/cache.c
>> @@ -61,8 +61,8 @@ int check_cache_range(unsigned long start, unsigned
>> long stop)
>>           ok = 0;
>>         if (!ok) {
>> -        debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
>> -              start, stop);
>> +        warn_non_spl("CACHE: Misaligned operation at range [%08lx,
>> %08lx]\n",
>> +                 start, stop);
>>       }
>>         return ok;
> Since this i've, and probably many others, have a bunch of warnings on
> doing something in u-boot.
> 
> Just compiled and installed today new u-boot on my zynq-board.
> 
> "
> U-Boot 2016.09-rc1-00353-g2ac625b-dirty (Aug 02 2016 - 08:06:57 +0200)
> 
> I2C:   ready
> DRAM:  ECC disabled 256 MiB
> MMC:   sdhci at e0100000: 0
> SF: Detected S25FL128S_64K with page size 256 Bytes, erase size 64 KiB,
> total 16 MiB
> FPGA:  id 0x2 (7z010)
> Net:   ZYNQ GEM: e000b000, phyaddr 0, interface rgmii-id
> *CACHE: Misaligned operation at range [0fff03b0, 0fff03b4]*
> 
> Warning: ethernet at e000b000 (eth0) using random MAC address -
> aa:99:75:dd:1d:71
> eth0: ethernet at e000b000
> SF: Detected S25FL128S_64K with page size 256 Bytes, erase size 64 KiB,
> total 16 MiB
> device 0 offset 0xc0000, size 0x10000
> SF: 65536 bytes @ 0xc0000 Read: OK
> ## Executing script at 000c0000
> => dhcp
> *CACHE: Misaligned operation at range [0eb583b0, 0eb583b4]**
> **CACHE: Misaligned operation at range [0eb583b4, 0eb583b8]*
> BOOTP broadcast 1
> BOOTP broadcast 2
> BOOTP broadcast 3
> DHCP client bound to address 192.168.21.193 (1008 ms)
> =>
> "
> 
> Do we have real trouble inside or can we quiet this warning?

I have seen it too. Look at gem driver which is flushing cache which is
not aligned. There must be some changes in the code to remove these
warnings. Also worth to add this to test/py to capture it in future.

Thanks,
Michal


-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP SoCs


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