[U-Boot] [PATCH] arm: cache: always flush cache line size for page table

[Marek Vasut]

On 08/02/2016 09:07 AM, Stefan Agner wrote:
> From: Stefan Agner <stefan.agner at toradex.com>
> 
> The page table is maintained by the CPU, hence it is safe to always
> align cache flush to a whole cache line size. This allows to use
> mmu_page_table_flush for a single page table, e.g. when configure
> only small regions through mmu_set_region_dcache_behaviour.
> 
> Signed-off-by: Stefan Agner <stefan.agner at toradex.com>
> ---
> This avoids two messages observed on a i.MX 7 based system:
> CACHE: Misaligned operation at range [9fff0000, 9fff0004]
> CACHE: Misaligned operation at range [9fff0024, 9fff0028]
> 
> Those were caused by two calls to mmu_set_region_dcache_behaviour
> in arch/arm/imx-common/cache.c (enable_caches).
> 
> Not sure if this is the right way to fix this... Also, we could
> do the alignment in mmu_set_region_dcache_behaviour.

This should be fixed on the driver level indeed, not in cache_v7.c

> --
> Stefan
> 
>  arch/arm/cpu/armv7/cache_v7.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
> index 52f1856..71787fc 100644
> --- a/arch/arm/cpu/armv7/cache_v7.c
> +++ b/arch/arm/cpu/armv7/cache_v7.c
> @@ -147,6 +147,13 @@ void arm_init_before_mmu(void)
>  
>  void mmu_page_table_flush(unsigned long start, unsigned long stop)
>  {
> +	/*
> +	 * Make sure range is cache line aligned
> +	 * Only CPU maintains page tables, hence it is save to always
> +	 * flush the complete cache line...
> +	 */
> +	start &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
> +	stop = ALIGN(stop, CONFIG_SYS_CACHELINE_SIZE);
>  	flush_dcache_range(start, stop);
>  	v7_inval_tlb();
>  }
> 


-- 
Best regards,
Marek Vasut