[U-Boot] [PATCH v3 6/6] xtensa: add support for the 'xtfpga' evaluation board

[Simon Glass]

On 5 August 2016 at 17:00, Max Filippov <jcmvbkbc at gmail.com> wrote:
> From: Chris Zankel <chris at zankel.net>
>
> The 'xtfpga' board is actually a set of FPGA evaluation boards that
> can be configured to run an Xtensa processor.
>
>  - Avnet Xilinx LX60
>  - Avnet Xilinx LX110
>  - Avnet Xilinx LX200
>  - Xilinx ML605
>  - Xilinx KC705
>
> These boards share the same components (open-ethernet, ns16550 serial,
> lcd display, flash, etc.).
>
> Signed-off-by: Chris Zankel <chris at zankel.net>
> Signed-off-by: Max Filippov <jcmvbkbc at gmail.com>
> ---
> Changes v2->v3:
> - drop LCD display support;
> - add reset driver;
> - add ethernet device configuration for DM_ETH driver;
> - enable phylib in defconfig;
> ---
>  arch/xtensa/Kconfig                    |   3 +
>  arch/xtensa/dts/Makefile               |   2 +
>  arch/xtensa/dts/kc705.dts              |  15 ++
>  arch/xtensa/dts/kc705_nommu.dts        |  17 +++
>  arch/xtensa/dts/ml605.dts              |  15 ++
>  arch/xtensa/dts/ml605_nommu.dts        |  18 +++
>  arch/xtensa/dts/xtfpga-flash-128m.dtsi |  28 ++++
>  arch/xtensa/dts/xtfpga-flash-16m.dtsi  |  28 ++++
>  arch/xtensa/dts/xtfpga.dtsi            | 137 +++++++++++++++++
>  board/cadence/xtfpga/Kconfig           |  39 +++++
>  board/cadence/xtfpga/MAINTAINERS       |   6 +
>  board/cadence/xtfpga/Makefile          |   7 +
>  board/cadence/xtfpga/README            | 125 +++++++++++++++
>  board/cadence/xtfpga/reset.c           |  35 +++++
>  board/cadence/xtfpga/xtfpga.c          | 115 ++++++++++++++
>  configs/xtfpga_defconfig               |  22 +++
>  include/configs/xtfpga.h               | 268 +++++++++++++++++++++++++++++++++
>  17 files changed, 880 insertions(+)
>  create mode 100644 arch/xtensa/dts/kc705.dts
>  create mode 100644 arch/xtensa/dts/kc705_nommu.dts
>  create mode 100644 arch/xtensa/dts/ml605.dts
>  create mode 100644 arch/xtensa/dts/ml605_nommu.dts
>  create mode 100644 arch/xtensa/dts/xtfpga-flash-128m.dtsi
>  create mode 100644 arch/xtensa/dts/xtfpga-flash-16m.dtsi
>  create mode 100644 arch/xtensa/dts/xtfpga.dtsi
>  create mode 100644 board/cadence/xtfpga/Kconfig
>  create mode 100644 board/cadence/xtfpga/MAINTAINERS
>  create mode 100644 board/cadence/xtfpga/Makefile
>  create mode 100644 board/cadence/xtfpga/README
>  create mode 100644 board/cadence/xtfpga/reset.c
>  create mode 100644 board/cadence/xtfpga/xtfpga.c
>  create mode 100644 configs/xtfpga_defconfig
>  create mode 100644 include/configs/xtfpga.h

Reviewed-by: Simon Glass <sjg at chromium.org>

nit: Your reset driver should really go in drivers/. Perhaps you could
create a new drivers/sysreset and put it there (in a follow-on patch
maybe). The existing sandbox, snapdragon and sysreset uclass could
move also.

- Simon