[U-Boot] [PATCH v3 1/6] xtensa: add support for the xtensa processor architecture [1/2]

[Tom Rini]

On Sat, Aug 06, 2016 at 02:00:39AM +0300, Max Filippov wrote:

> From: Chris Zankel <chris at zankel.net>
> 
> The Xtensa processor architecture is a configurable, extensible,
> and synthesizable 32-bit RISC processor core provided by Cadence.
> 
> This is the first part of the basic architecture port with changes to
> common files. The 'arch/xtensa' directory, and boards and additional
> drivers will be in separate commits.
> 
> Signed-off-by: Chris Zankel <chris at zankel.net>
> Signed-off-by: Max Filippov <jcmvbkbc at gmail.com>

Reviewed-by: Tom Rini <trini at konsulko.com>

-- 
Tom
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