[U-Boot] [RFC PATCH] ARM: cache: cp15: Align addresses when initial page_table setup is flushed

[Lukasz Majewski]

Hi Fabio,

> On Tue, Aug 9, 2016 at 5:41 AM, Lukasz Majewski
> <l.majewski at majess.pl> wrote:
> > Change made in the commit:
> > "arm: Show cache warnings in U-Boot proper only"
> > SHA1: bcc53bf095893fbdae531a9a7b5d4ef4a125a7fc
> >
> > has revealed that during initial setting of MMU regions in the
> > mmu_set_region_dcache_behavior() function some addresses are
> > unaligned to platform cache line size.
> >
> > As a result we were experiencing following warning messages at
> > early boot: CACHE: Misaligned operation at range [8fff0000,
> > 8fff0004] CACHE: Misaligned operation at range [8fff0024, 8fff0028]
> >
> > Those were caused by an attempt to update single page_table
> > (gd->arch.tlb_addr) entries with proper TLB cache settings.
> > Since TLB section covers large area (up to 2MiB), we had to update
> > very small amount of cache data, very often much smaller than
> > single cache line size (e.g. 32 or 64 bytes).
> >
> > This patch squashes this warning by properly aligning start and end
> > addresses. In fact it does what cache HW would do anyway (flush the
> > whole data cache lines).
> > Even without this patch it all worked, because TLB table sections
> > were initialized to default values earlier.
> >
> > Signed-off-by: Lukasz Majewski <l.majewski at majess.pl>
> 
> Stefan has also sent a patch for this:
> https://patchwork.ozlabs.org/patch/656470/

I see that I wasn't the only one.

Both patches are identical, Stefan was first :-)

My concern is that, as I've written with comment to my patch, that when
I was running build tests some other boards were broken since they
didn't define CONFIG_SYS_CACHELINE_SIZE.

Best regards,
Łukasz Majewski

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