[U-Boot] [PATCH v2 2/5] mpc85xx/powerpc:P1010: Apply errata A006261 for P1010

[Sriram Dash]

>From: york sun
>
>Sriram,
>
>Same comment here, please fix the subject.
>

Ok. Will modify patch title and commit message in v3.

>On 07/17/2016 08:47 PM, Sriram Dash wrote:
>> Apply USB errata A006261 for P1010.
>
>A006261 is already applied to P1010.
>
>
>>
>> Signed-off-by: Sriram Dash <sriram.dash at nxp.com>
>> Signed-off-by: Rajesh Bhagat <rajesh.bhagat at nxp.com>
>> ---
>>  arch/powerpc/include/asm/config_mpc85xx.h | 1 +
>>  arch/powerpc/include/asm/immap_85xx.h     | 2 ++
>>  2 files changed, 3 insertions(+)
>>
>> diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
>> b/arch/powerpc/include/asm/config_mpc85xx.h
>> index 505d355..9b7feda 100644
>> --- a/arch/powerpc/include/asm/config_mpc85xx.h
>> +++ b/arch/powerpc/include/asm/config_mpc85xx.h
>> @@ -162,6 +162,7 @@
>>  #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
>>  #define CONFIG_SYS_FSL_ERRATUM_A004508  #define
>> CONFIG_SYS_FSL_ERRATUM_A007075
>> +#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
>
>This is not enabling A006261. Please rewrite the commit message.
>

Ok. Will modify patch title and commit message in v3.

>>  #define CONFIG_SYS_FSL_ERRATUM_A006261  #define
>> CONFIG_SYS_FSL_ERRATUM_A004477
>>  #define CONFIG_SYS_FSL_A004447_SVR_REV	0x10
>> diff --git a/arch/powerpc/include/asm/immap_85xx.h
>> b/arch/powerpc/include/asm/immap_85xx.h
>> index c045a24..07ad22d 100644
>> --- a/arch/powerpc/include/asm/immap_85xx.h
>> +++ b/arch/powerpc/include/asm/immap_85xx.h
>> @@ -2953,6 +2953,8 @@ struct ccsr_pman {
>>  #define CONFIG_SYS_MPC85xx_DMA_OFFSET		0x21000
>>  #define CONFIG_SYS_MPC85xx_USB1_OFFSET		0x22000
>>  #define CONFIG_SYS_MPC85xx_USB2_OFFSET		0x23000
>> +#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET	0xE5000
>> +#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET	0xE5100
>
>This is not for the workaround.
>
>York
>

Ok. Will modify patch title and commit message in v3.

>
>>  #ifdef CONFIG_TSECV2
>>  #define CONFIG_SYS_TSEC1_OFFSET			0xB0000
>>  #elif defined(CONFIG_TSECV2_1)
>>