[U-Boot] ARM: non-sec: flush code cacheline aligned

[Tom Rini]

On Wed, Aug 03, 2016 at 01:08:55PM -0700, Stefan Agner wrote:

> From: Stefan Agner <stefan.agner at toradex.com>
> 
> Flush operations need to be cacheline aligned to take effect, make
> sure to flush always complete cachelines. This avoids messages such
> as:
> CACHE: Misaligned operation at range [00900000, 009004d9]
> 
> Signed-off-by: Stefan Agner <stefan.agner at toradex.com>
> Tested-by: Fabio Estevam <fabio.estevam at nxp.com>

Applied to u-boot/master, thanks!

-- 
Tom
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