[U-Boot] [PATCH v4] arm: cache: always flush cache line size for page table

[Tom Rini]

On Mon, Aug 08, 2016 at 12:43:03AM -0700, Stefan Agner wrote:
> On 2016-08-07 23:10, Lokesh Vutla wrote:
> > Hi,
> > 
> > On Sunday 07 August 2016 11:13 PM, Stefan Agner wrote:
> >> From: Stefan Agner <stefan.agner at toradex.com>
> >>
> >> The page table is maintained by the CPU, hence it is safe to always
> >> align cache flush to a whole cache line size. This allows to use
> >> mmu_page_table_flush for a single page table, e.g. when configure
> >> only small regions through mmu_set_region_dcache_behaviour.
> >>
> >> Signed-off-by: Stefan Agner <stefan.agner at toradex.com>
> >> Tested-by: Fabio Estevam <fabio.estevam at nxp.com>
> >> Reviewed-by: Simon Glass <sjg at chromium.org>
> >> ---
> > 
> > I get the following warning when CONFIG_PHYS_64BIT is enabled on arm
> > platforms(dra7xx_evm_defconfig):
> 
> Hm, do I see things right, this is otherwise a 32-bit architecture? Does
> that work without LPAE? What is the page table size in this case?

It's a 32bit architecture with LPAE, iirc, yes.

-- 
Tom
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