[U-Boot] [PATCH] drivers: usb: xhci-fsl: Change burst beat and outstanding pipelined transfers requests

[Marek Vasut]

On 08/19/2016 07:51 AM, Sriram Dash wrote:
> This is required for better performance, and performs below tuning:
> 1. Enable burst length set, and define it as 4/8/16.
> 2. Set burst request limit to 16 requests.
> 
> Signed-off-by: Rajesh Bhagat <rajesh.bhagat at nxp.com>
> Signed-off-by: Sriram Dash <sriram.dash at nxp.com>
> ---
>  drivers/usb/host/xhci-fsl.c  | 13 +++++++++++++
>  include/linux/usb/xhci-fsl.h |  3 +++
>  2 files changed, 16 insertions(+)
> 
> diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c
> index bdcd4f1..082924f 100644
> --- a/drivers/usb/host/xhci-fsl.c
> +++ b/drivers/usb/host/xhci-fsl.c
> @@ -58,6 +58,16 @@ static void fsl_apply_xhci_errata(void)
>  	}
>  }
>  
> +static void fsl_xhci_set_beat_burst_length(struct dwc3 *dwc3_reg)
> +{
> +	int val = readl(&dwc3_reg->g_sbuscfg0);
> +
> +	val &= ~USB3_ENABLE_BEAT_BURST_MASK;
> +	writel(val | USB3_ENABLE_BEAT_BURST, &dwc3_reg->g_sbuscfg0);
> +	val = readl(&dwc3_reg->g_sbuscfg1);
> +	writel(val | USB3_SET_BEAT_BURST_LIMIT, &dwc3_reg->g_sbuscfg1);

setbits_le32() ?

> +}
> +
>  static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
>  {
>  	int ret = 0;
> @@ -74,6 +84,9 @@ static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
>  	/* Set GFLADJ_30MHZ as 20h as per XHCI spec default value */
>  	dwc3_set_fladj(fsl_xhci->dwc3_reg, GFLADJ_30MHZ_DEFAULT);
>  
> +	/* Change beat burst and outstanding pipelined transfers requests */
> +	fsl_xhci_set_beat_burst_length(fsl_xhci->dwc3_reg);
> +
>  	return ret;
>  }
>  
> diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
> index 199f366..1032763 100644
> --- a/include/linux/usb/xhci-fsl.h
> +++ b/include/linux/usb/xhci-fsl.h
> @@ -20,6 +20,9 @@
>  #define USB3_PHY_TX_RX_POWERON	(USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON)
>  #define USB3_PWRCTL_CLK_CMD_SHIFT   14
>  #define USB3_PWRCTL_CLK_FREQ_SHIFT	22
> +#define USB3_ENABLE_BEAT_BURST		0xF
> +#define USB3_ENABLE_BEAT_BURST_MASK	0xFF
> +#define USB3_SET_BEAT_BURST_LIMIT	0xF00
>  
>  /* USBOTGSS_WRAPPER definitions */
>  #define USBOTGSS_WRAPRESET	BIT(17)
> 


-- 
Best regards,
Marek Vasut