[U-Boot] [PATCH 6/8] armv8: ls1046a: Enable DDR erratum for ls1046a

[Shengzhou Liu]

> -----Original Message-----
> From: Gong Qianyu [mailto:Qianyu.Gong at nxp.com]
> Sent: Friday, August 26, 2016 7:29 PM
> To: u-boot at lists.denx.de; york sun <york.sun at nxp.com>
> Cc: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>; Mingkai Hu
> <mingkai.hu at nxp.com>; Shaohui Xie <shaohui.xie at nxp.com>; Zhiqiang
> Hou <zhiqiang.hou at nxp.com>; Wenbin Song <wenbin.song at nxp.com>;
> Shengzhou Liu <shengzhou.liu at nxp.com>; Qianyu Gong
> <qianyu.gong at nxp.com>
> Subject: [PATCH 6/8] armv8: ls1046a: Enable DDR erratum for ls1046a
> 
> From: Shengzhou Liu <Shengzhou.Liu at nxp.com>
> 
> Enable ERRATUM_A009801, ERRATUM_A009803, ERRATUM_A009942,
> ERRATUM_A010165
> 
> Signed-off-by: Shengzhou Liu <Shengzhou.Liu at nxp.com>
> Signed-off-by: Gong Qianyu <Qianyu.Gong at nxp.com>
> ---
>  arch/arm/include/asm/arch-fsl-layerscape/config.h | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
> b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> index c7e374c..3250290 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> @@ -238,6 +238,11 @@
>  #define GICC_BASE		0x01420000
> 
>  #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
> +
> +#define CONFIG_SYS_FSL_ERRATUM_A009801
> +#define CONFIG_SYS_FSL_ERRATUM_A009803
> +#define CONFIG_SYS_FSL_ERRATUM_A009942
> +#define CONFIG_SYS_FSL_ERRATUM_A010165

LS1046 also need to enable ERRATUM_A008511 in this patch.