[U-Boot] [PATCH v4 1/4] mx6: ddr: Allow changing REFSEL and REFR fields

Eric Nelson eric at nelint.com
Tue Aug 30 02:34:01 CEST 2016


Hi Fabio,

On 08/29/2016 04:37 PM, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam at nxp.com>
> 
> Currently MX6 SPL DDR initialization hardcodes the REF_SEL and
> REFR fields of the MDREF register as 1 and 7, respectively for
> DDR3 and 0 and 3 for LPDDR2.
> 
> Looking at the MDREF initialization done via DCD we see that
> boards do need to initialize these fields differently:
> 
> $ git grep 0x021b0020 board/
> board/bachmann/ot1200/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
> board/ccv/xpress/imximage.cfg:DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */
> board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x7800
> board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x00005800
> board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
> board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
> board/freescale/mx6qsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00005800
> board/freescale/mx6qsabreauto/mx6dl.cfg:DATA 4 0x021b0020 0x00005800
> board/freescale/mx6qsabreauto/mx6qp.cfg:DATA 4 0x021b0020 0x00005800
> board/freescale/mx6sabresd/mx6dlsabresd.cfg:DATA 4      0x021b0020 0x00005800
> board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
> board/freescale/mx6slevk/imximage.cfg:DATA 4 0x021b0020 0x00001800
> board/freescale/mx6sxsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00000800
> board/freescale/mx6sxsabresd/imximage.cfg:DATA 4 0x021b0020 0x00000800
> board/warp/imximage.cfg:DATA 4 0x021b0020 0x00001800
> 
> So introduce a mechanism for users to be able to configure
> REFSEL and REFR fields as needed.
> 
> Keep all the mx6 SPL users in their current REF_SEL and REFR values,
> so no functional changes for the existing users.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam at nxp.com>
> ---
> Changes since v3:
> - Fix the logic for setting refsel/refr registers (Eric)
> 
>  arch/arm/cpu/armv7/mx6/ddr.c                      | 6 ++----
>  arch/arm/include/asm/arch-mx6/mx6-ddr.h           | 2 ++
>  board/bachmann/ot1200/ot1200_spl.c                | 2 ++
>  board/barco/platinum/spl_picon.c                  | 2 ++
>  board/barco/platinum/spl_titanium.c               | 2 ++
>  board/ccv/xpress/spl.c                            | 2 ++
>  board/compulab/cm_fx6/spl.c                       | 4 ++++
>  board/congatec/cgtqmx6eval/cgtqmx6eval.c          | 2 ++
>  board/el/el6x/el6x.c                              | 2 ++
>  board/freescale/mx6sabresd/mx6sabresd.c           | 2 ++
>  board/freescale/mx6slevk/mx6slevk.c               | 2 ++
>  board/freescale/mx6sxsabresd/mx6sxsabresd.c       | 2 ++
>  board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 4 ++++
>  board/gateworks/gw_ventana/gw_ventana_spl.c       | 2 ++
>  board/kosagi/novena/novena_spl.c                  | 2 ++
>  board/phytec/pcm058/pcm058.c                      | 2 ++
>  board/solidrun/mx6cuboxi/mx6cuboxi.c              | 2 ++
>  board/udoo/udoo_spl.c                             | 2 ++
>  board/wandboard/spl.c                             | 6 ++++++
>  19 files changed, 46 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
> index f151eec..7beb7ea 100644
> --- a/arch/arm/cpu/armv7/mx6/ddr.c
> +++ b/arch/arm/cpu/armv7/mx6/ddr.c
> @@ -1166,8 +1166,7 @@ void mx6_lpddr2_cfg(const struct mx6_ddr_sysinfo *sysinfo,
>  	mmdc0->mpzqhwctrl = val;
>  
>  	/* Step 12: Configure and activate periodic refresh */
> -	mmdc0->mdref = (0 << 14) | /* REF_SEL: Periodic refresh cycle: 64kHz */
> -		       (3 << 11);  /* REFR: Refresh Rate - 4 refreshes */
> +	mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11);
>  
>  	/* Step 13: Deassert config request - init complete */
>  	mmdc0->mdscr = 0x00000000;
> @@ -1472,8 +1471,7 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
>  		MMDC1(mpzqhwctrl, val);
>  
>  	/* Step 12: Configure and activate periodic refresh */
> -	mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */
> -		       (7 << 11);  /* REFR: Refresh Rate - 8 refreshes */
> +	mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11);
>  
>  	/* Step 13: Deassert config request - init complete */
>  	mmdc0->mdscr = 0x00000000;
> diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
> index 12c30d2..9922409 100644
> --- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
> +++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
> @@ -408,6 +408,8 @@ struct mx6_ddr_sysinfo {
>  	u8 sde_to_rst;	/* Time from SDE enable until DDR reset# is high */
>  	u8 pd_fast_exit;/* enable precharge powerdown fast-exit */
>  	u8 ddr_type;	/* DDR type: DDR3(0) or LPDDR2(1) */
> +	u8 refsel;	/* REF_SEL field of register MDREF */
> +	u8 refr;	/* REFR field of register MDREF */
>  };
>  
>  /*
> diff --git a/board/bachmann/ot1200/ot1200_spl.c b/board/bachmann/ot1200/ot1200_spl.c
> index f651a40..9d28da4 100644
> --- a/board/bachmann/ot1200/ot1200_spl.c
> +++ b/board/bachmann/ot1200/ot1200_spl.c
> @@ -85,6 +85,8 @@ static struct mx6_ddr_sysinfo ot1200_ddr_sysinfo = {
>  	.bi_on      = 1,	/* Bank interleaving enabled */	/* war 1 */
>  	.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
>  	.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
> +	.refsel = 1,		/* Refresh cycles at 32KHz */
> +	.refr = 7,		/* 8 refresh commands per refresh cycle */
>  };
>  
>  /* MT41K128M16JT-125 */
> diff --git a/board/barco/platinum/spl_picon.c b/board/barco/platinum/spl_picon.c
> index 098542f..97a861f 100644
> --- a/board/barco/platinum/spl_picon.c
> +++ b/board/barco/platinum/spl_picon.c
> @@ -138,6 +138,8 @@ static void spl_dram_init(int width)
>  		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
>  		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
>  		.ddr_type = DDR_TYPE_DDR3,
> +		.refsel = 1,	/* Refresh cycles at 32KHz */
> +		.refr = 7, 	/* 8 refresh commands per refresh cycle */
>  	};
>  
>  	mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
> diff --git a/board/barco/platinum/spl_titanium.c b/board/barco/platinum/spl_titanium.c
> index a3a4255..d1ba85a 100644
> --- a/board/barco/platinum/spl_titanium.c
> +++ b/board/barco/platinum/spl_titanium.c
> @@ -141,6 +141,8 @@ static void spl_dram_init(int width)
>  		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
>  		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
>  		.ddr_type = DDR_TYPE_DDR3,
> +		.refsel = 1,		/* Refresh cycles at 32KHz */
> +		.refr = 7,		/* 8 refresh commands per refresh cycle */
>  	};
>  
>  	mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
> diff --git a/board/ccv/xpress/spl.c b/board/ccv/xpress/spl.c
> index d15b842..bea837d 100644
> --- a/board/ccv/xpress/spl.c
> +++ b/board/ccv/xpress/spl.c
> @@ -60,6 +60,8 @@ struct mx6_ddr_sysinfo ddr_sysinfo = {
>  	.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
>  	.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
>  	.ddr_type = DDR_TYPE_DDR3,
> +	.refsel = 1,		/* Refresh cycles at 32KHz */
> +	.refr = 7,		/* 8 refresh commands per refresh cycle */
>  };
>  
>  static struct mx6_ddr3_cfg mem_ddr = {
> diff --git a/board/compulab/cm_fx6/spl.c b/board/compulab/cm_fx6/spl.c
> index d8328fd..9442d09 100644
> --- a/board/compulab/cm_fx6/spl.c
> +++ b/board/compulab/cm_fx6/spl.c
> @@ -107,6 +107,8 @@ static struct mx6_ddr_sysinfo cm_fx6_sysinfo_s = {
>  	.mif3_mode	= 3,
>  	.rst_to_cke	= 0x23,
>  	.sde_to_rst	= 0x10,
> +	.refsel = 1,		/* Refresh cycles at 32KHz */
> +	.refr = 7,		/* 8 refresh commands per refresh cycle */
>  };
>  
>  static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_s = {
> @@ -174,6 +176,8 @@ static struct mx6_ddr_sysinfo cm_fx6_sysinfo_q = {
>  	.mif3_mode	= 3,
>  	.rst_to_cke	= 0x23,
>  	.sde_to_rst	= 0x10,
> +	.refsel = 1,		/* Refresh cycles at 32KHz */
> +	.refr = 7,		/* 8 refresh commands per refresh cycle */
>  };
>  
>  static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_q = {
> diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c
> index 3fbd3d2..a4a6029 100644
> --- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c
> +++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c
> @@ -1037,6 +1037,8 @@ static void spl_dram_init(int width)
>  		.bi_on = 1,
>  		.sde_to_rst = 0x0d,
>  		.rst_to_cke = 0x20,
> +		.refsel = 1,	/* Refresh cycles at 32KHz */
> +		.refr = 7,	/* 8 refresh commands per refresh cycle */
>  	};
>  
>  	if (is_cpu_type(MXC_CPU_MX6Q) && is_2gb()) {
> diff --git a/board/el/el6x/el6x.c b/board/el/el6x/el6x.c
> index 3b0fb32..7856b84 100644
> --- a/board/el/el6x/el6x.c
> +++ b/board/el/el6x/el6x.c
> @@ -604,6 +604,8 @@ static void spl_dram_init(void)
>  		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
>  		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
>  		.ddr_type = DDR_TYPE_DDR3,
> +		.refsel = 1,	/* Refresh cycles at 32KHz */
> +		.refr = 7,	/* 8 refresh commands per refresh cycle */
>  	};
>  
>  	mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
> diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
> index 0cf6809..f836ecb 100644
> --- a/board/freescale/mx6sabresd/mx6sabresd.c
> +++ b/board/freescale/mx6sabresd/mx6sabresd.c
> @@ -854,6 +854,8 @@ static void spl_dram_init(void)
>  		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
>  		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
>  		.ddr_type = DDR_TYPE_DDR3,
> +		.refsel = 1,	/* Refresh cycles at 32KHz */
> +		.refr = 7,	/* 8 refresh commands per refresh cycle */
>  	};
>  
>  	if (is_mx6dqp()) {
> diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
> index f978e50..96c0e8c 100644
> --- a/board/freescale/mx6slevk/mx6slevk.c
> +++ b/board/freescale/mx6slevk/mx6slevk.c
> @@ -494,6 +494,8 @@ static void spl_dram_init(void)
>  		.sde_to_rst = 0,    /* LPDDR2 does not need this field */
>  		.rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
>  		.ddr_type = DDR_TYPE_LPDDR2,
> +		.refsel = 0,	/* Refresh cycles at 64KHz */
> +		.refr = 3,	/* 4 refresh commands per refresh cycle */
>  	};
>  	mx6sl_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
>  	mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
> diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
> index 8d95c51..965e511 100644
> --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
> +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
> @@ -637,6 +637,8 @@ static void spl_dram_init(void)
>  		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
>  		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
>  		.ddr_type = DDR_TYPE_DDR3,
> +		.refsel = 1,	/* Refresh cycles at 32KHz */
> +		.refr = 7,	/* 8 refresh commands per refresh cycle */
>  	};
>  
>  	mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
> diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
> index c213861..5e39108 100644
> --- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
> +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
> @@ -766,6 +766,8 @@ struct mx6_ddr_sysinfo ddr_sysinfo = {
>  	.sde_to_rst = 0,    /* LPDDR2 does not need this field */
>  	.rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
>  	.ddr_type = DDR_TYPE_LPDDR2,
> +	.refsel = 0,	/* Refresh cycles at 64KHz */
> +	.refr = 3,	/* 4 refresh commands per refresh cycle */
>  };
>  
>  #else
> @@ -804,6 +806,8 @@ struct mx6_ddr_sysinfo ddr_sysinfo = {
>  	.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
>  	.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
>  	.ddr_type = DDR_TYPE_DDR3,
> +	.refsel = 1,	/* Refresh cycles at 32KHz */
> +	.refr = 7,	/* 8 refresh commands per refresh cycle */
>  };
>  
>  static struct mx6_ddr3_cfg mem_ddr = {
> diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c
> index e7f699a..b610e06 100644
> --- a/board/gateworks/gw_ventana/gw_ventana_spl.c
> +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c
> @@ -394,6 +394,8 @@ static void spl_dram_init(int width, int size_mb, int board_model)
>  		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
>  		.pd_fast_exit = 1, /* enable precharge power-down fast exit */
>  		.ddr_type = DDR_TYPE_DDR3,
> +		.refsel = 1,	/* Refresh cycles at 32KHz */
> +		.refr = 7,	/* 8 refresh commands per refresh cycle */
>  	};
>  
>  	/*
> diff --git a/board/kosagi/novena/novena_spl.c b/board/kosagi/novena/novena_spl.c
> index f779bb4..92c61ae 100644
> --- a/board/kosagi/novena/novena_spl.c
> +++ b/board/kosagi/novena/novena_spl.c
> @@ -520,6 +520,8 @@ static struct mx6_ddr_sysinfo novena_ddr_info = {
>  	.bi_on		= 1,	/* Bank interleaving enabled */
>  	.sde_to_rst	= 0x10,	/* 14 cycles, 200us (JEDEC default) */
>  	.rst_to_cke	= 0x23,	/* 33 cycles, 500us (JEDEC default) */
> +	.refsel = 1,	/* Refresh cycles at 32KHz */
> +	.refr = 7,	/* 8 refresh commands per refresh cycle */
>  };
>  
>  static struct mx6_ddr3_cfg elpida_4gib_1600 = {
> diff --git a/board/phytec/pcm058/pcm058.c b/board/phytec/pcm058/pcm058.c
> index 0ba4a2e..4e2122f 100644
> --- a/board/phytec/pcm058/pcm058.c
> +++ b/board/phytec/pcm058/pcm058.c
> @@ -521,6 +521,8 @@ static void spl_dram_init(void)
>  		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
>  		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
>  		.ddr_type = DDR_TYPE_DDR3,
> +		.refsel = 1,	/* Refresh cycles at 32KHz */
> +		.refr = 7,	/* 8 refresh commands per refresh cycle */
>  	};
>  
>  	mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
> diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c
> index cafa348..3a1ce24 100644
> --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
> +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
> @@ -605,6 +605,8 @@ static void spl_dram_init(int width)
>  		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
>  		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
>  		.ddr_type = DDR_TYPE_DDR3,
> +		.refsel = 1,	/* Refresh cycles at 32KHz */
> +		.refr = 7,	/* 8 refresh commands per refresh cycle */
>  	};
>  
>  	if (is_mx6dq())
> diff --git a/board/udoo/udoo_spl.c b/board/udoo/udoo_spl.c
> index a1154ed..592e69b 100644
> --- a/board/udoo/udoo_spl.c
> +++ b/board/udoo/udoo_spl.c
> @@ -193,6 +193,8 @@ static struct mx6_ddr_sysinfo mem_qdl = {
>  	.mif3_mode = 3,
>  	.rst_to_cke = 0x23,
>  	.sde_to_rst = 0x10,
> +	.refsel = 1,	/* Refresh cycles at 32KHz */
> +	.refr = 7,	/* 8 refresh commands per refresh cycle */
>  };
>  
>  static void ccgr_init(void)
> diff --git a/board/wandboard/spl.c b/board/wandboard/spl.c
> index 77afae7..085095c 100644
> --- a/board/wandboard/spl.c
> +++ b/board/wandboard/spl.c
> @@ -187,6 +187,8 @@ static struct mx6_ddr_sysinfo mem_q = {
>  	.mif3_mode	= 3,
>  	.rst_to_cke	= 0x23,
>  	.sde_to_rst	= 0x10,
> +	.refsel = 1,	/* Refresh cycles at 32KHz */
> +	.refr = 7,	/* 8 refresh commands per refresh cycle */
>  };
>  
>  static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
> @@ -228,6 +230,8 @@ static struct mx6_ddr_sysinfo mem_dl = {
>  	.mif3_mode	= 3,
>  	.rst_to_cke	= 0x23,
>  	.sde_to_rst	= 0x10,
> +	.refsel = 1,	/* Refresh cycles at 32KHz */
> +	.refr = 7,	/* 8 refresh commands per refresh cycle */
>  };
>  
>  /* DDR 32bit 512MB */
> @@ -245,6 +249,8 @@ static struct mx6_ddr_sysinfo mem_s = {
>  	.mif3_mode	= 3,
>  	.rst_to_cke	= 0x23,
>  	.sde_to_rst	= 0x10,
> +	.refsel = 1,	/* Refresh cycles at 32KHz */
> +	.refr = 7,	/* 8 refresh commands per refresh cycle */
>  };
>  
>  static void ccgr_init(void)
> 

Reviewed-by: Eric Nelson <eric at nelint.com>


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