[U-Boot] [PATCH 3/8] armv8: fsl-layerscape: Increase L2 Data RAM latency and L2 Tag RAM latency

[Mingkai Hu]

> -----Original Message-----
> From: york sun
> Sent: Friday, August 26, 2016 11:01 PM
> To: Qianyu Gong <qianyu.gong at nxp.com>; u-boot at lists.denx.de
> Cc: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>; Mingkai Hu
> <mingkai.hu at nxp.com>; Shaohui Xie <shaohui.xie at nxp.com>; Zhiqiang Hou
> <zhiqiang.hou at nxp.com>; Wenbin Song <wenbin.song at nxp.com>
> Subject: Re: [PATCH 3/8] armv8: fsl-layerscape: Increase L2 Data RAM latency
> and L2 Tag RAM latency
> 
> On 08/26/2016 04:40 AM, Gong Qianyu wrote:
> > From: Mingkai Hu <mingkai.hu at nxp.com>
> >
> > Use 3 cycles.
> 
> Care to explain more here?
> 

Hi York,

According to design, the L2 cache operates at the same frequency as the A72 CPUs in the cluster with a 3-cycle latency,
So increase the L2 Data RAM and Tag RAM latency to 3 cycles, or else, will run into different call trace issues.

Thanks,
Mingkai