[U-Boot] [PATCH] mpc85xx: pci: Implement workaround for Erratum A007815

[Chris Packham]

(adding York)

On Thu, Dec 1, 2016 at 4:20 PM, Tony O'Brien
<tony.obrien at alliedtelesis.co.nz> wrote:
> The read-only-write-enable bit is set by default and must be cleared
> to prevent overwriting read-only registers.  This should be done
> immediately after resetting the PCI Express controller.
>
> Reviewed-by: Hamish Martin <hamish.martin at alliedtelesis.co.nz>
>
> ---
> Note that this does not implement the whole fix for this erratum,
> just what is necessary for our implementation. Since we are using a
> fixed RC configuration, no support has been added for EP mode or any
> consideration of link-up/down events.
>
> Signed-off-by: Tony O'Brien <tony.obrien at alliedtelesis.co.nz>
> ---
>  arch/powerpc/cpu/mpc85xx/cmd_errata.c     | 3 +++
>  arch/powerpc/include/asm/config_mpc85xx.h | 1 +
>  arch/powerpc/include/asm/fsl_pci.h        | 4 +++-
>  drivers/pci/fsl_pci_init.c                | 7 +++++++
>  4 files changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
> index 402a1ff..aabb56b 100644
> --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
> +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
> @@ -330,6 +330,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
>  #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
>         puts("Work-around for Erratum A009663 enabled\n");
>  #endif
> +#ifdef CONFIG_SYS_FSL_ERRATUM_A007815
> +       puts("Work-around for Erratum A007815 enabled\n");
> +#endif
>
>         return 0;
>  }
> diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
> index c92bc1e..c298e44 100644
> --- a/arch/powerpc/include/asm/config_mpc85xx.h
> +++ b/arch/powerpc/include/asm/config_mpc85xx.h
> @@ -785,6 +785,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
>  #define CONFIG_SYS_FSL_ERRATUM_A006593
>  #define CONFIG_SYS_FSL_ERRATUM_A007186
>  #define CONFIG_SYS_FSL_ERRATUM_A006379
> +#define CONFIG_SYS_FSL_ERRATUM_A007815
>  #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
>  #define CONFIG_SYS_FSL_SFP_VER_3_0
>
> diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h
> index 8bee8ca..cad341e 100644
> --- a/arch/powerpc/include/asm/fsl_pci.h
> +++ b/arch/powerpc/include/asm/fsl_pci.h
> @@ -79,7 +79,9 @@ typedef struct ccsr_pci {
>         u32     pme_msg_dis;    /* 0x024 - PCIE PME & message disable register */
>         u32     pme_msg_int_en; /* 0x028 - PCIE PME & message interrupt enable register */
>         u32     pm_command;     /* 0x02c - PCIE PM Command register */
> -       char    res4[3016];     /*     (- #xbf8  #x30)3016 */
> +       char    res3[2188];     /*     (0x8bc - 0x30 = 2188) */
> +       u32     dbi_ro_wr_en;   /* 0x8bc - DBI read only write enable reg */
> +       char    res4[824];      /*     (0xbf8 - 0x8c0 = 824) */
>         u32     block_rev1;     /* 0xbf8 - PCIE Block Revision register 1 */
>         u32     block_rev2;     /* 0xbfc - PCIE Block Revision register 2 */
>
> diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
> index 52792dc..af20cf0 100644
> --- a/drivers/pci/fsl_pci_init.c
> +++ b/drivers/pci/fsl_pci_init.c
> @@ -543,6 +543,13 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
>                 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
>         }
>
> +#ifdef CONFIG_SYS_FSL_ERRATUM_A007815
> +       /* The Read-Only Write Enable bit defaults to 1 instead of 0.
> +        * Set to 0 to protect the read-only registers.
> +        */
> +       clrbits_be32(&pci->dbi_ro_wr_en, 0x01);
> +#endif
> +
>         /* Use generic setup_device to initialize standard pci regs,
>          * but do not allocate any windows since any BAR found (such
>          * as PCSRBAR) is not in this cpu's memory space.
> --
> 2.10.2
>
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