[U-Boot] [PATCH v3 2/9] ARM: DTS: stm32: add stm32f746-disco device tree files
vikas
vikas.manocha at st.com
Thu Dec 1 19:00:45 CET 2016
Hi Michael,
On 11/24/2016 11:10 AM, Michael Kurz wrote:
> This patch adds the DTS source files needed for stm32f746-disco board
> The files are based on the stm32f429/469 files from current linux
> kernel.
>
> Signed-off-by: Michael Kurz <michi.kurz at gmail.com>
> Acked-by: Vikas MANOCHA <vikas.manocha at st.com>
>
> ---
>
> Changes in v3:
> - Split pin control files of from device tree patch
> - Add Acked-by tag to 'add stm32f746-disco device tree files'
>
> Changes in v2: None
>
> arch/arm/dts/Makefile | 2 +
> arch/arm/dts/armv7-m.dtsi | 24 +++
> arch/arm/dts/stm32f746-disco.dts | 154 +++++++++++++++
> arch/arm/dts/stm32f746.dtsi | 397 ++++++++++++++++++++++++++++++++++++++
> configs/stm32f746-disco_defconfig | 1 +
> 5 files changed, 578 insertions(+)
> create mode 100644 arch/arm/dts/armv7-m.dtsi
> create mode 100644 arch/arm/dts/stm32f746-disco.dts
> create mode 100644 arch/arm/dts/stm32f746.dtsi
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 2c5b2f2..b340f82 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -157,6 +157,8 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
>
> dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
>
> +dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb
> +
> dtb-$(CONFIG_MACH_SUN4I) += \
> sun4i-a10-a1000.dtb \
> sun4i-a10-ba10-tvbox.dtb \
> diff --git a/arch/arm/dts/armv7-m.dtsi b/arch/arm/dts/armv7-m.dtsi
> new file mode 100644
> index 0000000..e0a6bf2
> --- /dev/null
> +++ b/arch/arm/dts/armv7-m.dtsi
> @@ -0,0 +1,24 @@
> +#include "skeleton.dtsi"
> +
> +/ {
> + nvic: interrupt-controller at e000e100 {
> + compatible = "arm,armv7m-nvic";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + reg = <0xe000e100 0xc00>;
> + };
> +
[...]
> + pin-controller {
> + usart1_pins_disco: usart1 at 0 {
> + pins1 {
> + pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
> + bias-disable;
> + drive-push-pull;
> + slew-rate = <0>;
> + };
> + pins2 {
> + pinmux = <STM32F746_PA10_FUNC_USART1_RX>;
should be PB7_xxx for stm32f7 board.
> + bias-disable;
> + };
> + };
> +
> + ethernet_pins_disco: ethernet at 0 {
> + pins {
> + pinmux = <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
> + <STM32F746_PA2_FUNC_ETH_MDIO>,
> + <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
> + <STM32F746_PC1_FUNC_ETH_MDC>,
> + <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
> + <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>,
> + <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
> + <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
> + <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>;
do we need to add RMII_RXER (optional).
> + slew-rate = <2>;
> + };
> + };
> +
> + qspi_pins_disco: qspi at 0 {
> + pins {
> + pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>,
> + <STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>,
> + <STM32F746_PD11_FUNC_QUADSPI_BK1_IO0>,
> + <STM32F746_PD12_FUNC_QUADSPI_BK1_IO1>,
> + <STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>,
> + <STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>;
> + slew-rate = <2>;
> + };
> + };
> + };
> + };
> +};
> +
> +&clk_hse {
> + clock-frequency = <25000000>;
> +};
> +
> +&mac {
> + status = "okay";
> + pinctrl-0 = <ðernet_pins_disco>;
> + pinctrl-names = "default";
> + phy-mode = "rmii";
> + phy-handle = <&phy0>;
> + mdio0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "snps,dwmac-mdio";
> + phy0: ethernet-phy at 0 {
> + reg = <0>;
> + };
> + };
> +};
> +
> +&usart1 {
> + pinctrl-0 = <&usart1_pins_disco>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
[...]
> + gpiok: gpio at 40022800 {
> + gpio-controller;
> + #gpio-cells = <2>;
> + reg = <0x2800 0x400>;
> + clocks = <&rcc 0 10>;
> + st,bank-name = "GPIOK";
> + };
> + };
> +
> + rcc: rcc at 40023810 {
> + #reset-cells = <1>;
> + #clock-cells = <2>;
> + compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
f42xx ?
> + reg = <0x40023800 0x400>;
> + clocks = <&clk_hse>;
> + };
> +
> + dma1: dma-controller at 40026000 {
> + compatible = "st,stm32-dma";
> + reg = <0x40026000 0x400>;
> + interrupts = <11>,
> + <12>,
> + <13>,
> + <14>,
> + <15>,
> + <16>,
> + <17>,
> + <47>;
> + clocks = <&rcc 0 21>;
> + #dma-cells = <4>;
> + };
> +
> + dma2: dma-controller at 40026400 {
> + compatible = "st,stm32-dma";
> + reg = <0x40026400 0x400>;
> + interrupts = <56>,
> + <57>,
> + <58>,
> + <59>,
> + <60>,
> + <68>,
> + <69>,
> + <70>;
> + clocks = <&rcc 0 22>;
> + #dma-cells = <4>;
> + st,mem2mem;
> + };
> +
> + mac: ethernet at 40028000 {
> + compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
dwmac-3.50a is not a valid compatible string in u-boot...
It is the problem of copying soc linux device tree file to u-boot, its good to be in sync with linux dts but it is not one to one map yet.
I would suggest to copy the part which makes sense (like ethernet & qspi) for this patchset and remove others like usb, gpio, dma, timers, u(s)art etc. Otherwise we would need to clean it later to make dts compatible with u-boot drivers.
> + reg = <0x40028000 0x8000>;
> + reg-names = "stmmaceth";
> + interrupts = <61>, <62>;
> + interrupt-names = "macirq", "eth_wake_irq";
> + clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
> + clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
> + st,syscon = <&syscfg 0x4>;
> + snps,pbl = <8>;
> + snps,mixed-burst;
> + dma-ranges;
> + status = "disabled";
> + };
> +
> + usbotg_hs: usb at 40040000 {
> + compatible = "snps,dwc2";
> + dma-ranges;
[...]
Cheers,
Vikas
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