[U-Boot] [PATCH 4/4] ARM: dts: uniphier: sync Device Tree with Linux

[Masahiro Yamada]

Signed-off-by: Masahiro Yamada <yamada.masahiro at socionext.com>
---

 arch/arm/dts/uniphier-common32.dtsi   | 177 -------
 arch/arm/dts/uniphier-ld11.dtsi       | 111 +++-
 arch/arm/dts/uniphier-ld20.dtsi       | 188 +++++--
 arch/arm/dts/uniphier-ld4.dtsi        | 652 ++++++++++++++----------
 arch/arm/dts/uniphier-pro4-ref.dts    |  10 +-
 arch/arm/dts/uniphier-pro4.dtsi       | 903 +++++++++++++++++++--------------
 arch/arm/dts/uniphier-pro5.dtsi       | 925 +++++++++++++++++++++-------------
 arch/arm/dts/uniphier-pxs2-gentil.dts |   2 +-
 arch/arm/dts/uniphier-pxs2-vodka.dts  |   2 +-
 arch/arm/dts/uniphier-pxs2.dtsi       | 878 +++++++++++++++++++-------------
 arch/arm/dts/uniphier-sld3.dtsi       |  37 +-
 arch/arm/dts/uniphier-sld8.dtsi       | 650 ++++++++++++++----------
 12 files changed, 2684 insertions(+), 1851 deletions(-)
 delete mode 100644 arch/arm/dts/uniphier-common32.dtsi

diff --git a/arch/arm/dts/uniphier-common32.dtsi b/arch/arm/dts/uniphier-common32.dtsi
deleted file mode 100644
index f87e320..0000000
--- a/arch/arm/dts/uniphier-common32.dtsi
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * Device Tree Source commonly used by UniPhier ARM SoCs
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro at socionext.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+	X11
- */
-
-/include/ "skeleton.dtsi"
-
-/ {
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
-	clocks {
-		refclk: ref {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-		};
-	};
-
-	soc: soc {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-		interrupt-parent = <&intc>;
-		u-boot,dm-pre-reloc;
-
-		serial0: serial at 54006800 {
-			compatible = "socionext,uniphier-uart";
-			status = "disabled";
-			reg = <0x54006800 0x40>;
-			interrupts = <0 33 4>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_uart0>;
-			clocks = <&peri_clk 0>;
-		};
-
-		serial1: serial at 54006900 {
-			compatible = "socionext,uniphier-uart";
-			status = "disabled";
-			reg = <0x54006900 0x40>;
-			interrupts = <0 35 4>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_uart1>;
-			clocks = <&peri_clk 1>;
-		};
-
-		serial2: serial at 54006a00 {
-			compatible = "socionext,uniphier-uart";
-			status = "disabled";
-			reg = <0x54006a00 0x40>;
-			interrupts = <0 37 4>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_uart2>;
-			clocks = <&peri_clk 2>;
-		};
-
-		serial3: serial at 54006b00 {
-			compatible = "socionext,uniphier-uart";
-			status = "disabled";
-			reg = <0x54006b00 0x40>;
-			interrupts = <0 177 4>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_uart3>;
-			clocks = <&peri_clk 3>;
-		};
-
-		system_bus: system-bus at 58c00000 {
-			compatible = "socionext,uniphier-system-bus";
-			status = "disabled";
-			reg = <0x58c00000 0x400>;
-			#address-cells = <2>;
-			#size-cells = <1>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_system_bus>;
-		};
-
-		smpctrl at 59800000 {
-			compatible = "socionext,uniphier-smpctrl";
-			reg = <0x59801000 0x400>;
-		};
-
-		mioctrl at 59810000 {
-			compatible = "socionext,uniphier-mioctrl",
-				     "simple-mfd", "syscon";
-			reg = <0x59810000 0x800>;
-			u-boot,dm-pre-reloc;
-
-			mio_clk: clock {
-				#clock-cells = <1>;
-			};
-
-			mio_rst: reset {
-				#reset-cells = <1>;
-			};
-		};
-
-		perictrl at 59820000 {
-			compatible = "socionext,uniphier-perictrl",
-				     "simple-mfd", "syscon";
-			reg = <0x59820000 0x200>;
-
-			peri_clk: clock {
-				#clock-cells = <1>;
-			};
-
-			peri_rst: reset {
-				#reset-cells = <1>;
-			};
-		};
-
-		timer at 60000200 {
-			compatible = "arm,cortex-a9-global-timer";
-			reg = <0x60000200 0x20>;
-			interrupts = <1 11 0x104>;
-			clocks = <&arm_timer_clk>;
-		};
-
-		timer at 60000600 {
-			compatible = "arm,cortex-a9-twd-timer";
-			reg = <0x60000600 0x20>;
-			interrupts = <1 13 0x104>;
-			clocks = <&arm_timer_clk>;
-		};
-
-		intc: interrupt-controller at 60001000 {
-			compatible = "arm,cortex-a9-gic";
-			reg = <0x60001000 0x1000>,
-			      <0x60000100 0x100>;
-			#interrupt-cells = <3>;
-			interrupt-controller;
-		};
-
-		soc-glue at 5f800000 {
-			compatible = "socionext,uniphier-soc-glue",
-				     "simple-mfd", "syscon";
-			reg = <0x5f800000 0x2000>;
-			u-boot,dm-pre-reloc;
-
-			pinctrl: pinctrl {
-				/* specify compatible in each SoC DTSI */
-				u-boot,dm-pre-reloc;
-			};
-		};
-
-		sysctrl at 61840000 {
-			compatible = "socionext,uniphier-sysctrl",
-				     "simple-mfd", "syscon";
-			reg = <0x61840000 0x4000>;
-
-			sys_clk: clock {
-				#clock-cells = <1>;
-			};
-
-			sys_rst: reset {
-				#reset-cells = <1>;
-			};
-		};
-
-		nand: nand at 68000000 {
-			compatible = "denali,denali-nand-dt";
-			status = "disabled";
-			reg-names = "nand_data", "denali_reg";
-			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
-			interrupts = <0 65 4>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_nand>;
-		};
-	};
-};
-
-/include/ "uniphier-pinctrl.dtsi"
diff --git a/arch/arm/dts/uniphier-ld11.dtsi b/arch/arm/dts/uniphier-ld11.dtsi
index a95cb6e..eef4dce 100644
--- a/arch/arm/dts/uniphier-ld11.dtsi
+++ b/arch/arm/dts/uniphier-ld11.dtsi
@@ -7,7 +7,7 @@
  * SPDX-License-Identifier:	GPL-2.0+	X11
  */
 
-/memreserve/ 0x80000000 0x00000008;	/* cpu-release-addr */
+/memreserve/ 0x80000000 0x00080000;
 
 / {
 	compatible = "socionext,uniphier-ld11";
@@ -34,31 +34,66 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0 0x000>;
-			enable-method = "spin-table";
-			cpu-release-addr = <0 0x80000000>;
+			clocks = <&sys_clk 33>;
+			enable-method = "psci";
+			operating-points-v2 = <&cluster0_opp>;
 		};
 
 		cpu1: cpu at 1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0 0x001>;
-			enable-method = "spin-table";
-			cpu-release-addr = <0 0x80000000>;
+			clocks = <&sys_clk 33>;
+			enable-method = "psci";
+			operating-points-v2 = <&cluster0_opp>;
 		};
 	};
 
+	cluster0_opp: opp_table {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp at 245000000 {
+			opp-hz = /bits/ 64 <245000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 250000000 {
+			opp-hz = /bits/ 64 <250000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 490000000 {
+			opp-hz = /bits/ 64 <490000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 653334000 {
+			opp-hz = /bits/ 64 <653334000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 666667000 {
+			opp-hz = /bits/ 64 <666667000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 980000000 {
+			opp-hz = /bits/ 64 <980000000>;
+			clock-latency-ns = <300>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
 	clocks {
 		refclk: ref {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			clock-frequency = <25000000>;
 		};
-
-		i2c_clk: i2c_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <50000000>;
-		};
 	};
 
 	timer {
@@ -129,7 +164,7 @@
 			interrupts = <0 41 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_i2c0>;
-			clocks = <&i2c_clk>;
+			clocks = <&peri_clk 4>;
 			clock-frequency = <100000>;
 		};
 
@@ -142,7 +177,7 @@
 			interrupts = <0 42 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_i2c1>;
-			clocks = <&i2c_clk>;
+			clocks = <&peri_clk 5>;
 			clock-frequency = <100000>;
 		};
 
@@ -152,7 +187,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			interrupts = <0 43 4>;
-			clocks = <&i2c_clk>;
+			clocks = <&peri_clk 6>;
 			clock-frequency = <400000>;
 		};
 
@@ -165,7 +200,7 @@
 			interrupts = <0 44 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_i2c3>;
-			clocks = <&i2c_clk>;
+			clocks = <&peri_clk 7>;
 			clock-frequency = <100000>;
 		};
 
@@ -178,7 +213,7 @@
 			interrupts = <0 45 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_i2c4>;
-			clocks = <&i2c_clk>;
+			clocks = <&peri_clk 8>;
 			clock-frequency = <100000>;
 		};
 
@@ -188,7 +223,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			interrupts = <0 25 4>;
-			clocks = <&i2c_clk>;
+			clocks = <&peri_clk 9>;
 			clock-frequency = <400000>;
 		};
 
@@ -207,8 +242,19 @@
 			reg = <0x59801000 0x400>;
 		};
 
+		sdctrl at 59810000 {
+			compatible = "socionext,uniphier-ld11-sdctrl",
+				     "simple-mfd", "syscon";
+			reg = <0x59810000 0x400>;
+
+			sd_rst: reset {
+				compatible = "socionext,uniphier-ld11-sd-reset";
+				#reset-cells = <1>;
+			};
+		};
+
 		perictrl at 59820000 {
-			compatible = "socionext,uniphier-perictrl",
+			compatible = "socionext,uniphier-ld11-perictrl",
 				     "simple-mfd", "syscon";
 			reg = <0x59820000 0x200>;
 
@@ -223,6 +269,19 @@
 			};
 		};
 
+		emmc: sdhc at 5a000000 {
+			compatible = "cdns,sd4hc";
+			reg = <0x5a000000 0x400>;
+			interrupts = <0 78 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_emmc_1v8>;
+			clocks = <&sys_clk 4>;
+			bus-width = <8>;
+			mmc-ddr-1_8v;
+			mmc-hs200-1_8v;
+			/* mmc-hs400-1_8v; support depends on board design */
+		};
+
 		usb0: usb at 5a800100 {
 			compatible = "socionext,uniphier-ehci", "generic-ehci";
 			status = "disabled";
@@ -277,7 +336,7 @@
 		};
 
 		soc-glue at 5f800000 {
-			compatible = "socionext,uniphier-soc-glue",
+			compatible = "socionext,uniphier-ld11-soc-glue",
 				     "simple-mfd", "syscon";
 			reg = <0x5f800000 0x2000>;
 			u-boot,dm-pre-reloc;
@@ -305,7 +364,7 @@
 		sysctrl at 61840000 {
 			compatible = "socionext,uniphier-ld11-sysctrl",
 				     "simple-mfd", "syscon";
-			reg = <0x61840000 0x4000>;
+			reg = <0x61840000 0x10000>;
 
 			sys_clk: clock {
 				compatible = "socionext,uniphier-ld11-clock";
@@ -317,6 +376,18 @@
 				#reset-cells = <1>;
 			};
 		};
+
+		nand: nand at 68000000 {
+			compatible = "socionext,denali-nand-v5b";
+			status = "disabled";
+			reg-names = "nand_data", "denali_reg";
+			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+			interrupts = <0 65 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_nand>;
+			clocks = <&sys_clk 2>;
+			nand-ecc-strength = <8>;
+		};
 	};
 };
 
diff --git a/arch/arm/dts/uniphier-ld20.dtsi b/arch/arm/dts/uniphier-ld20.dtsi
index 29a84ae..1b41945 100644
--- a/arch/arm/dts/uniphier-ld20.dtsi
+++ b/arch/arm/dts/uniphier-ld20.dtsi
@@ -7,7 +7,7 @@
  * SPDX-License-Identifier:	GPL-2.0+	X11
  */
 
-/memreserve/ 0x80000000 0x00000008;	/* cpu-release-addr */
+/memreserve/ 0x80000000 0x00080000;
 
 / {
 	compatible = "socionext,uniphier-ld20";
@@ -43,47 +43,126 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a72", "arm,armv8";
 			reg = <0 0x000>;
-			enable-method = "spin-table";
-			cpu-release-addr = <0 0x80000000>;
+			clocks = <&sys_clk 32>;
+			enable-method = "psci";
+			operating-points-v2 = <&cluster0_opp>;
 		};
 
 		cpu1: cpu at 1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a72", "arm,armv8";
 			reg = <0 0x001>;
-			enable-method = "spin-table";
-			cpu-release-addr = <0 0x80000000>;
+			clocks = <&sys_clk 32>;
+			enable-method = "psci";
+			operating-points-v2 = <&cluster0_opp>;
 		};
 
 		cpu2: cpu at 100 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0 0x100>;
-			enable-method = "spin-table";
-			cpu-release-addr = <0 0x80000000>;
+			clocks = <&sys_clk 33>;
+			enable-method = "psci";
+			operating-points-v2 = <&cluster1_opp>;
 		};
 
 		cpu3: cpu at 101 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0 0x101>;
-			enable-method = "spin-table";
-			cpu-release-addr = <0 0x80000000>;
+			clocks = <&sys_clk 33>;
+			enable-method = "psci";
+			operating-points-v2 = <&cluster1_opp>;
 		};
 	};
 
+	cluster0_opp: opp_table0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp at 250000000 {
+			opp-hz = /bits/ 64 <250000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 275000000 {
+			opp-hz = /bits/ 64 <275000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 550000000 {
+			opp-hz = /bits/ 64 <550000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 666667000 {
+			opp-hz = /bits/ 64 <666667000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 733334000 {
+			opp-hz = /bits/ 64 <733334000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 1100000000 {
+			opp-hz = /bits/ 64 <1100000000>;
+			clock-latency-ns = <300>;
+		};
+	};
+
+	cluster1_opp: opp_table1 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp at 250000000 {
+			opp-hz = /bits/ 64 <250000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 275000000 {
+			opp-hz = /bits/ 64 <275000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 550000000 {
+			opp-hz = /bits/ 64 <550000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 666667000 {
+			opp-hz = /bits/ 64 <666667000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 733334000 {
+			opp-hz = /bits/ 64 <733334000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 1100000000 {
+			opp-hz = /bits/ 64 <1100000000>;
+			clock-latency-ns = <300>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
 	clocks {
 		refclk: ref {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			clock-frequency = <25000000>;
 		};
-
-		i2c_clk: i2c_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <50000000>;
-		};
 	};
 
 	timer {
@@ -154,7 +233,7 @@
 			interrupts = <0 41 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_i2c0>;
-			clocks = <&i2c_clk>;
+			clocks = <&peri_clk 4>;
 			clock-frequency = <100000>;
 		};
 
@@ -167,7 +246,7 @@
 			interrupts = <0 42 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_i2c1>;
-			clocks = <&i2c_clk>;
+			clocks = <&peri_clk 5>;
 			clock-frequency = <100000>;
 		};
 
@@ -177,7 +256,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			interrupts = <0 43 4>;
-			clocks = <&i2c_clk>;
+			clocks = <&peri_clk 6>;
 			clock-frequency = <400000>;
 		};
 
@@ -190,7 +269,7 @@
 			interrupts = <0 44 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_i2c3>;
-			clocks = <&i2c_clk>;
+			clocks = <&peri_clk 7>;
 			clock-frequency = <100000>;
 		};
 
@@ -203,7 +282,7 @@
 			interrupts = <0 45 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_i2c4>;
-			clocks = <&i2c_clk>;
+			clocks = <&peri_clk 8>;
 			clock-frequency = <100000>;
 		};
 
@@ -213,7 +292,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			interrupts = <0 25 4>;
-			clocks = <&i2c_clk>;
+			clocks = <&peri_clk 9>;
 			clock-frequency = <400000>;
 		};
 
@@ -232,24 +311,24 @@
 			reg = <0x59801000 0x400>;
 		};
 
-		mioctrl at 59810000 {
-			compatible = "socionext,uniphier-mioctrl",
+		sdctrl at 59810000 {
+			compatible = "socionext,uniphier-ld20-sdctrl",
 				     "simple-mfd", "syscon";
 			reg = <0x59810000 0x800>;
 
-			mio_clk: clock {
-				compatible = "socionext,uniphier-ld20-mio-clock";
+			sd_clk: clock {
+				compatible = "socionext,uniphier-ld20-sd-clock";
 				#clock-cells = <1>;
 			};
 
-			mio_rst: reset {
-				compatible = "socionext,uniphier-ld20-mio-reset";
+			sd_rst: reset {
+				compatible = "socionext,uniphier-ld20-sd-reset";
 				#reset-cells = <1>;
 			};
 		};
 
 		perictrl at 59820000 {
-			compatible = "socionext,uniphier-perictrl",
+			compatible = "socionext,uniphier-ld20-perictrl",
 				     "simple-mfd", "syscon";
 			reg = <0x59820000 0x200>;
 
@@ -264,6 +343,19 @@
 			};
 		};
 
+		emmc: sdhc at 5a000000 {
+			compatible = "cdns,sd4hc";
+			reg = <0x5a000000 0x400>;
+			interrupts = <0 78 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_emmc_1v8>;
+			clocks = <&sys_clk 4>;
+			bus-width = <8>;
+			mmc-ddr-1_8v;
+			mmc-hs200-1_8v;
+			/* mmc-hs400-1_8v; support depends on board design */
+		};
+
 		sd: sdhc at 5a400000 {
 			compatible = "socionext,uniphier-sdhc";
 			status = "disabled";
@@ -271,14 +363,15 @@
 			interrupts = <0 76 4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_sd>;
-			clocks = <&mio_clk 0>;
+			clocks = <&sd_clk 0>;
 			reset-names = "host";
-			resets = <&mio_rst 0>;
+			resets = <&sd_rst 0>;
 			bus-width = <4>;
+			cap-sd-highspeed;
 		};
 
 		soc-glue at 5f800000 {
-			compatible = "socionext,uniphier-soc-glue",
+			compatible = "socionext,uniphier-ld20-soc-glue",
 				     "simple-mfd", "syscon";
 			reg = <0x5f800000 0x2000>;
 			u-boot,dm-pre-reloc;
@@ -304,9 +397,9 @@
 		};
 
 		sysctrl at 61840000 {
-			compatible = "socionext,uniphier-sysctrl",
+			compatible = "socionext,uniphier-ld20-sysctrl",
 				     "simple-mfd", "syscon";
-			reg = <0x61840000 0x4000>;
+			reg = <0x61840000 0x10000>;
 
 			sys_clk: clock {
 				compatible = "socionext,uniphier-ld20-clock";
@@ -318,6 +411,35 @@
 				#reset-cells = <1>;
 			};
 		};
+
+		usb: usb at 65b00000 {
+			compatible = "socionext,uniphier-ld20-dwc3";
+			reg = <0x65b00000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
+				    <&pinctrl_usb2>, <&pinctrl_usb3>;
+			dwc3 at 65a00000 {
+				compatible = "snps,dwc3";
+				reg = <0x65a00000 0x10000>;
+				interrupts = <0 134 4>;
+				tx-fifo-resize;
+			};
+		};
+
+		nand: nand at 68000000 {
+			compatible = "socionext,denali-nand-v5b";
+			status = "disabled";
+			reg-names = "nand_data", "denali_reg";
+			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+			interrupts = <0 65 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_nand>;
+			clocks = <&sys_clk 2>;
+			nand-ecc-strength = <8>;
+		};
 	};
 };
 
diff --git a/arch/arm/dts/uniphier-ld4.dtsi b/arch/arm/dts/uniphier-ld4.dtsi
index 9f555df..2f8ecad 100644
--- a/arch/arm/dts/uniphier-ld4.dtsi
+++ b/arch/arm/dts/uniphier-ld4.dtsi
@@ -7,7 +7,7 @@
  * SPDX-License-Identifier:	GPL-2.0+	X11
  */
 
-/include/ "uniphier-common32.dtsi"
+/include/ "skeleton.dtsi"
 
 / {
 	compatible = "socionext,uniphier-ld4";
@@ -25,313 +25,439 @@
 		};
 	};
 
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
 	clocks {
-		arm_timer_clk: arm_timer_clk {
-			#clock-cells = <0>;
+		refclk: ref {
 			compatible = "fixed-clock";
-			clock-frequency = <50000000>;
+			#clock-cells = <0>;
+			clock-frequency = <24576000>;
 		};
 
-		iobus_clk: iobus_clk {
+		arm_timer_clk: arm_timer_clk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
-			clock-frequency = <100000000>;
+			clock-frequency = <50000000>;
 		};
 	};
-};
 
-&soc {
-	l2: l2-cache at 500c0000 {
-		compatible = "socionext,uniphier-system-cache";
-		reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
-		interrupts = <0 174 4>, <0 175 4>;
-		cache-unified;
-		cache-size = <(512 * 1024)>;
-		cache-sets = <256>;
-		cache-line-size = <128>;
-		cache-level = <2>;
-	};
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		interrupt-parent = <&intc>;
+		u-boot,dm-pre-reloc;
+
+		l2: l2-cache at 500c0000 {
+			compatible = "socionext,uniphier-system-cache";
+			reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
+			      <0x506c0000 0x400>;
+			interrupts = <0 174 4>, <0 175 4>;
+			cache-unified;
+			cache-size = <(512 * 1024)>;
+			cache-sets = <256>;
+			cache-line-size = <128>;
+			cache-level = <2>;
+		};
 
-	port0x: gpio at 55000008 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000008 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		serial0: serial at 54006800 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006800 0x40>;
+			interrupts = <0 33 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart0>;
+			clocks = <&peri_clk 0>;
+			clock-frequency = <36864000>;
+		};
 
-	port1x: gpio at 55000010 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000010 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		serial1: serial at 54006900 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006900 0x40>;
+			interrupts = <0 35 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart1>;
+			clocks = <&peri_clk 1>;
+			clock-frequency = <36864000>;
+		};
 
-	port2x: gpio at 55000018 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000018 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		serial2: serial at 54006a00 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006a00 0x40>;
+			interrupts = <0 37 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart2>;
+			clocks = <&peri_clk 2>;
+			clock-frequency = <36864000>;
+		};
 
-	port3x: gpio at 55000020 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000020 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		serial3: serial at 54006b00 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006b00 0x40>;
+			interrupts = <0 29 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart3>;
+			clocks = <&peri_clk 3>;
+			clock-frequency = <36864000>;
+		};
 
-	port4: gpio at 55000028 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000028 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port0x: gpio at 55000008 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000008 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port5x: gpio at 55000030 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000030 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port1x: gpio at 55000010 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000010 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port6x: gpio at 55000038 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000038 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port2x: gpio at 55000018 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000018 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port7x: gpio at 55000040 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000040 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port3x: gpio at 55000020 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000020 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port8x: gpio at 55000048 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000048 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port4: gpio at 55000028 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000028 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port9x: gpio at 55000050 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000050 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port5x: gpio at 55000030 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000030 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port10x: gpio at 55000058 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000058 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port6x: gpio at 55000038 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000038 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port11x: gpio at 55000060 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000060 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port7x: gpio at 55000040 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000040 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port12x: gpio at 55000068 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000068 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port8x: gpio at 55000048 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000048 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port13x: gpio at 55000070 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000070 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port9x: gpio at 55000050 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000050 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port14x: gpio at 55000078 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000078 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port10x: gpio at 55000058 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000058 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port16x: gpio at 55000088 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000088 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port11x: gpio at 55000060 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000060 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	i2c0: i2c at 58400000 {
-		compatible = "socionext,uniphier-i2c";
-		status = "disabled";
-		reg = <0x58400000 0x40>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 41 1>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c0>;
-		clocks = <&iobus_clk>;
-		clock-frequency = <100000>;
-	};
+		port12x: gpio at 55000068 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000068 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	i2c1: i2c at 58480000 {
-		compatible = "socionext,uniphier-i2c";
-		status = "disabled";
-		reg = <0x58480000 0x40>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 42 1>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c1>;
-		clocks = <&iobus_clk>;
-		clock-frequency = <100000>;
-	};
+		port13x: gpio at 55000070 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000070 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	/* chip-internal connection for DMD */
-	i2c2: i2c at 58500000 {
-		compatible = "socionext,uniphier-i2c";
-		reg = <0x58500000 0x40>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 43 1>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c2>;
-		clocks = <&iobus_clk>;
-		clock-frequency = <400000>;
-	};
+		port14x: gpio at 55000078 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000078 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	i2c3: i2c at 58580000 {
-		compatible = "socionext,uniphier-i2c";
-		status = "disabled";
-		reg = <0x58580000 0x40>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 44 1>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c3>;
-		clocks = <&iobus_clk>;
-		clock-frequency = <100000>;
-	};
+		port16x: gpio at 55000088 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000088 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	sd: sdhc at 5a400000 {
-		compatible = "socionext,uniphier-sdhc";
-		status = "disabled";
-		reg = <0x5a400000 0x200>;
-		interrupts = <0 76 4>;
-		pinctrl-names = "default", "1.8v";
-		pinctrl-0 = <&pinctrl_sd>;
-		pinctrl-1 = <&pinctrl_sd_1v8>;
-		clocks = <&mio_clk 0>;
-		reset-names = "host", "bridge";
-		resets = <&mio_rst 0>, <&mio_rst 3>;
-		bus-width = <4>;
-	};
+		i2c0: i2c at 58400000 {
+			compatible = "socionext,uniphier-i2c";
+			status = "disabled";
+			reg = <0x58400000 0x40>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 41 1>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c0>;
+			clocks = <&peri_clk 4>;
+			clock-frequency = <100000>;
+		};
 
-	emmc: sdhc at 5a500000 {
-		compatible = "socionext,uniphier-sdhc";
-		status = "disabled";
-		reg = <0x5a500000 0x200>;
-		interrupts = <0 78 4>;
-		pinctrl-names = "default", "1.8v";
-		pinctrl-0 = <&pinctrl_emmc>;
-		pinctrl-1 = <&pinctrl_emmc_1v8>;
-		clocks = <&mio_clk 1>;
-		reset-names = "host", "bridge", "hw-reset";
-		resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
-		bus-width = <8>;
-		non-removable;
-	};
+		i2c1: i2c at 58480000 {
+			compatible = "socionext,uniphier-i2c";
+			status = "disabled";
+			reg = <0x58480000 0x40>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 42 1>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c1>;
+			clocks = <&peri_clk 5>;
+			clock-frequency = <100000>;
+		};
 
-	usb0: usb at 5a800100 {
-		compatible = "socionext,uniphier-ehci", "generic-ehci";
-		status = "disabled";
-		reg = <0x5a800100 0x100>;
-		interrupts = <0 80 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_usb0>;
-		clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
-		resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
-			 <&mio_rst 12>;
-	};
+		/* chip-internal connection for DMD */
+		i2c2: i2c at 58500000 {
+			compatible = "socionext,uniphier-i2c";
+			reg = <0x58500000 0x40>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 43 1>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c2>;
+			clocks = <&peri_clk 6>;
+			clock-frequency = <400000>;
+		};
 
-	usb1: usb at 5a810100 {
-		compatible = "socionext,uniphier-ehci", "generic-ehci";
-		status = "disabled";
-		reg = <0x5a810100 0x100>;
-		interrupts = <0 81 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_usb1>;
-		clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
-		resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
-			 <&mio_rst 13>;
-	};
+		i2c3: i2c at 58580000 {
+			compatible = "socionext,uniphier-i2c";
+			status = "disabled";
+			reg = <0x58580000 0x40>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 44 1>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c3>;
+			clocks = <&peri_clk 7>;
+			clock-frequency = <100000>;
+		};
 
-	usb2: usb at 5a820100 {
-		compatible = "socionext,uniphier-ehci", "generic-ehci";
-		status = "disabled";
-		reg = <0x5a820100 0x100>;
-		interrupts = <0 82 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_usb2>;
-		clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
-		resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
-			 <&mio_rst 14>;
-	};
+		system_bus: system-bus at 58c00000 {
+			compatible = "socionext,uniphier-system-bus";
+			status = "disabled";
+			reg = <0x58c00000 0x400>;
+			#address-cells = <2>;
+			#size-cells = <1>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_system_bus>;
+		};
 
-	aidet at 61830000 {
-		compatible = "simple-mfd", "syscon";
-		reg = <0x61830000 0x200>;
-	};
-};
+		smpctrl at 59800000 {
+			compatible = "socionext,uniphier-smpctrl";
+			reg = <0x59801000 0x400>;
+		};
 
-&refclk {
-	clock-frequency = <24576000>;
-};
+		mioctrl at 59810000 {
+			compatible = "socionext,uniphier-ld4-mioctrl",
+				     "simple-mfd", "syscon";
+			reg = <0x59810000 0x800>;
+			u-boot,dm-pre-reloc;
+
+			mio_clk: clock {
+				compatible = "socionext,uniphier-ld4-mio-clock";
+				#clock-cells = <1>;
+			};
+
+			mio_rst: reset {
+				compatible = "socionext,uniphier-ld4-mio-reset";
+				#reset-cells = <1>;
+			};
+		};
 
-&serial0 {
-	clock-frequency = <36864000>;
-};
+		perictrl at 59820000 {
+			compatible = "socionext,uniphier-ld4-perictrl",
+				     "simple-mfd", "syscon";
+			reg = <0x59820000 0x200>;
 
-&serial1 {
-	clock-frequency = <36864000>;
-};
+			peri_clk: clock {
+				compatible = "socionext,uniphier-ld4-peri-clock";
+				#clock-cells = <1>;
+			};
 
-&serial2 {
-	clock-frequency = <36864000>;
-};
+			peri_rst: reset {
+				compatible = "socionext,uniphier-ld4-peri-reset";
+				#reset-cells = <1>;
+			};
+		};
 
-&serial3 {
-	interrupts = <0 29 4>;
-	clock-frequency = <36864000>;
-};
+		sd: sdhc at 5a400000 {
+			compatible = "socionext,uniphier-sdhc";
+			status = "disabled";
+			reg = <0x5a400000 0x200>;
+			interrupts = <0 76 4>;
+			pinctrl-names = "default", "1.8v";
+			pinctrl-0 = <&pinctrl_sd>;
+			pinctrl-1 = <&pinctrl_sd_1v8>;
+			clocks = <&mio_clk 0>;
+			reset-names = "host", "bridge";
+			resets = <&mio_rst 0>, <&mio_rst 3>;
+			bus-width = <4>;
+			cap-sd-highspeed;
+			sd-uhs-sdr12;
+			sd-uhs-sdr25;
+			sd-uhs-sdr50;
+		};
 
-&mio_clk {
-	compatible = "socionext,uniphier-ld4-mio-clock";
-};
+		emmc: sdhc at 5a500000 {
+			compatible = "socionext,uniphier-sdhc";
+			status = "disabled";
+			reg = <0x5a500000 0x200>;
+			interrupts = <0 78 4>;
+			pinctrl-names = "default", "1.8v";
+			pinctrl-0 = <&pinctrl_emmc>;
+			pinctrl-1 = <&pinctrl_emmc_1v8>;
+			clocks = <&mio_clk 1>;
+			reset-names = "host", "bridge";
+			resets = <&mio_rst 1>, <&mio_rst 4>;
+			bus-width = <8>;
+			non-removable;
+			cap-mmc-highspeed;
+			cap-mmc-hw-reset;
+		};
 
-&mio_rst {
-	compatible = "socionext,uniphier-ld4-mio-reset";
-};
+		usb0: usb at 5a800100 {
+			compatible = "socionext,uniphier-ehci", "generic-ehci";
+			status = "disabled";
+			reg = <0x5a800100 0x100>;
+			interrupts = <0 80 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb0>;
+			clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
+			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
+				 <&mio_rst 12>;
+		};
 
-&peri_clk {
-	compatible = "socionext,uniphier-ld4-peri-clock";
-};
+		usb1: usb at 5a810100 {
+			compatible = "socionext,uniphier-ehci", "generic-ehci";
+			status = "disabled";
+			reg = <0x5a810100 0x100>;
+			interrupts = <0 81 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb1>;
+			clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
+			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
+				 <&mio_rst 13>;
+		};
 
-&peri_rst {
-	compatible = "socionext,uniphier-ld4-peri-reset";
-};
+		usb2: usb at 5a820100 {
+			compatible = "socionext,uniphier-ehci", "generic-ehci";
+			status = "disabled";
+			reg = <0x5a820100 0x100>;
+			interrupts = <0 82 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb2>;
+			clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
+			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
+				 <&mio_rst 14>;
+		};
 
-&pinctrl {
-	compatible = "socionext,uniphier-ld4-pinctrl";
-};
+		soc-glue at 5f800000 {
+			compatible = "socionext,uniphier-ld4-soc-glue",
+				     "simple-mfd", "syscon";
+			reg = <0x5f800000 0x2000>;
+			u-boot,dm-pre-reloc;
 
-&sys_clk {
-	compatible = "socionext,uniphier-ld4-clock";
-};
+			pinctrl: pinctrl {
+				compatible = "socionext,uniphier-ld4-pinctrl";
+				u-boot,dm-pre-reloc;
+			};
+		};
+
+		timer at 60000200 {
+			compatible = "arm,cortex-a9-global-timer";
+			reg = <0x60000200 0x20>;
+			interrupts = <1 11 0x104>;
+			clocks = <&arm_timer_clk>;
+		};
 
-&sys_rst {
-	compatible = "socionext,uniphier-ld4-reset";
+		timer at 60000600 {
+			compatible = "arm,cortex-a9-twd-timer";
+			reg = <0x60000600 0x20>;
+			interrupts = <1 13 0x104>;
+			clocks = <&arm_timer_clk>;
+		};
+
+		intc: interrupt-controller at 60001000 {
+			compatible = "arm,cortex-a9-gic";
+			reg = <0x60001000 0x1000>,
+			      <0x60000100 0x100>;
+			#interrupt-cells = <3>;
+			interrupt-controller;
+		};
+
+		aidet at 61830000 {
+			compatible = "simple-mfd", "syscon";
+			reg = <0x61830000 0x200>;
+		};
+
+		sysctrl at 61840000 {
+			compatible = "socionext,uniphier-ld4-sysctrl",
+				     "simple-mfd", "syscon";
+			reg = <0x61840000 0x10000>;
+
+			sys_clk: clock {
+				compatible = "socionext,uniphier-ld4-clock";
+				#clock-cells = <1>;
+			};
+
+			sys_rst: reset {
+				compatible = "socionext,uniphier-ld4-reset";
+				#reset-cells = <1>;
+			};
+		};
+
+		nand: nand at 68000000 {
+			compatible = "socionext,denali-nand-v5a";
+			status = "disabled";
+			reg-names = "nand_data", "denali_reg";
+			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+			interrupts = <0 65 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_nand>;
+			clocks = <&sys_clk 2>;
+			nand-ecc-strength = <8>;
+		};
+	};
 };
+
+/include/ "uniphier-pinctrl.dtsi"
diff --git a/arch/arm/dts/uniphier-pro4-ref.dts b/arch/arm/dts/uniphier-pro4-ref.dts
index 2d49b3e..9714fb0 100644
--- a/arch/arm/dts/uniphier-pro4-ref.dts
+++ b/arch/arm/dts/uniphier-pro4-ref.dts
@@ -68,15 +68,19 @@
 	status = "okay";
 };
 
-&usb0 {
+&usb2 {
 	status = "okay";
 };
 
-&usb2 {
+&usb3 {
 	status = "okay";
 };
 
-&usb3 {
+&usb0 {
+	status = "okay";
+};
+
+&usb1 {
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/uniphier-pro4.dtsi b/arch/arm/dts/uniphier-pro4.dtsi
index aa80ea4..9b881f6 100644
--- a/arch/arm/dts/uniphier-pro4.dtsi
+++ b/arch/arm/dts/uniphier-pro4.dtsi
@@ -7,7 +7,7 @@
  * SPDX-License-Identifier:	GPL-2.0+	X11
  */
 
-/include/ "uniphier-common32.dtsi"
+/include/ "skeleton.dtsi"
 
 / {
 	compatible = "socionext,uniphier-pro4";
@@ -33,452 +33,593 @@
 		};
 	};
 
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
 	clocks {
+		refclk: ref {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <25000000>;
+		};
+
 		arm_timer_clk: arm_timer_clk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <50000000>;
 		};
+	};
 
-		uart_clk: uart_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		interrupt-parent = <&intc>;
+		u-boot,dm-pre-reloc;
+
+		l2: l2-cache at 500c0000 {
+			compatible = "socionext,uniphier-system-cache";
+			reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
+			      <0x506c0000 0x400>;
+			interrupts = <0 174 4>, <0 175 4>;
+			cache-unified;
+			cache-size = <(768 * 1024)>;
+			cache-sets = <256>;
+			cache-line-size = <128>;
+			cache-level = <2>;
+		};
+
+		serial0: serial at 54006800 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006800 0x40>;
+			interrupts = <0 33 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart0>;
+			clocks = <&peri_clk 0>;
 			clock-frequency = <73728000>;
 		};
 
-		i2c_clk: i2c_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <50000000>;
+		serial1: serial at 54006900 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006900 0x40>;
+			interrupts = <0 35 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart1>;
+			clocks = <&peri_clk 1>;
+			clock-frequency = <73728000>;
 		};
-	};
-};
 
-&soc {
-	l2: l2-cache at 500c0000 {
-		compatible = "socionext,uniphier-system-cache";
-		reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
-		interrupts = <0 174 4>, <0 175 4>;
-		cache-unified;
-		cache-size = <(768 * 1024)>;
-		cache-sets = <256>;
-		cache-line-size = <128>;
-		cache-level = <2>;
-	};
+		serial2: serial at 54006a00 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006a00 0x40>;
+			interrupts = <0 37 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart2>;
+			clocks = <&peri_clk 2>;
+			clock-frequency = <73728000>;
+		};
 
-	port0x: gpio at 55000008 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000008 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		serial3: serial at 54006b00 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006b00 0x40>;
+			interrupts = <0 177 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart3>;
+			clocks = <&peri_clk 3>;
+			clock-frequency = <73728000>;
+		};
 
-	port1x: gpio at 55000010 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000010 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port0x: gpio at 55000008 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000008 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port2x: gpio at 55000018 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000018 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port1x: gpio at 55000010 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000010 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port3x: gpio at 55000020 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000020 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port2x: gpio at 55000018 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000018 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port4: gpio at 55000028 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000028 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port3x: gpio at 55000020 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000020 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port5x: gpio at 55000030 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000030 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port4: gpio at 55000028 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000028 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port6x: gpio at 55000038 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000038 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port5x: gpio at 55000030 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000030 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port7x: gpio at 55000040 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000040 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port6x: gpio at 55000038 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000038 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port8x: gpio at 55000048 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000048 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port7x: gpio at 55000040 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000040 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port9x: gpio at 55000050 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000050 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port8x: gpio at 55000048 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000048 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port10x: gpio at 55000058 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000058 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port9x: gpio at 55000050 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000050 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port11x: gpio at 55000060 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000060 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port10x: gpio at 55000058 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000058 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port12x: gpio at 55000068 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000068 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port11x: gpio at 55000060 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000060 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port13x: gpio at 55000070 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000070 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port12x: gpio at 55000068 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000068 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port14x: gpio at 55000078 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000078 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port13x: gpio at 55000070 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000070 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port17x: gpio at 550000a0 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000a0 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port14x: gpio at 55000078 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000078 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port18x: gpio at 550000a8 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000a8 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port17x: gpio at 550000a0 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000a0 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port19x: gpio at 550000b0 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000b0 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port18x: gpio at 550000a8 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000a8 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port20x: gpio at 550000b8 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000b8 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port19x: gpio at 550000b0 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000b0 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port21x: gpio at 550000c0 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000c0 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port20x: gpio at 550000b8 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000b8 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port22x: gpio at 550000c8 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000c8 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port21x: gpio at 550000c0 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000c0 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port23x: gpio at 550000d0 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000d0 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port22x: gpio at 550000c8 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000c8 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port24x: gpio at 550000d8 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000d8 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port23x: gpio at 550000d0 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000d0 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port25x: gpio at 550000e0 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000e0 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port24x: gpio at 550000d8 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000d8 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port26x: gpio at 550000e8 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000e8 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port25x: gpio at 550000e0 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000e0 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port27x: gpio at 550000f0 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000f0 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port26x: gpio at 550000e8 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000e8 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port28x: gpio at 550000f8 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000f8 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port27x: gpio at 550000f0 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000f0 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port29x: gpio at 55000100 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000100 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port28x: gpio at 550000f8 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000f8 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port30x: gpio at 55000108 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000108 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port29x: gpio at 55000100 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000100 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	i2c0: i2c at 58780000 {
-		compatible = "socionext,uniphier-fi2c";
-		status = "disabled";
-		reg = <0x58780000 0x80>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 41 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c0>;
-		clocks = <&i2c_clk>;
-		clock-frequency = <100000>;
-	};
+		port30x: gpio at 55000108 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000108 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	i2c1: i2c at 58781000 {
-		compatible = "socionext,uniphier-fi2c";
-		status = "disabled";
-		reg = <0x58781000 0x80>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 42 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c1>;
-		clocks = <&i2c_clk>;
-		clock-frequency = <100000>;
-	};
+		i2c0: i2c at 58780000 {
+			compatible = "socionext,uniphier-fi2c";
+			status = "disabled";
+			reg = <0x58780000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 41 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c0>;
+			clocks = <&peri_clk 4>;
+			clock-frequency = <100000>;
+		};
 
-	i2c2: i2c at 58782000 {
-		compatible = "socionext,uniphier-fi2c";
-		status = "disabled";
-		reg = <0x58782000 0x80>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 43 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c2>;
-		clocks = <&i2c_clk>;
-		clock-frequency = <100000>;
-	};
+		i2c1: i2c at 58781000 {
+			compatible = "socionext,uniphier-fi2c";
+			status = "disabled";
+			reg = <0x58781000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 42 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c1>;
+			clocks = <&peri_clk 5>;
+			clock-frequency = <100000>;
+		};
 
-	i2c3: i2c at 58783000 {
-		compatible = "socionext,uniphier-fi2c";
-		status = "disabled";
-		reg = <0x58783000 0x80>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 44 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c3>;
-		clocks = <&i2c_clk>;
-		clock-frequency = <100000>;
-	};
+		i2c2: i2c at 58782000 {
+			compatible = "socionext,uniphier-fi2c";
+			status = "disabled";
+			reg = <0x58782000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 43 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c2>;
+			clocks = <&peri_clk 6>;
+			clock-frequency = <100000>;
+		};
 
-	/* i2c4 does not exist */
+		i2c3: i2c at 58783000 {
+			compatible = "socionext,uniphier-fi2c";
+			status = "disabled";
+			reg = <0x58783000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 44 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c3>;
+			clocks = <&peri_clk 7>;
+			clock-frequency = <100000>;
+		};
 
-	/* chip-internal connection for DMD */
-	i2c5: i2c at 58785000 {
-		compatible = "socionext,uniphier-fi2c";
-		reg = <0x58785000 0x80>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 25 4>;
-		clocks = <&i2c_clk>;
-		clock-frequency = <400000>;
-	};
+		/* i2c4 does not exist */
+
+		/* chip-internal connection for DMD */
+		i2c5: i2c at 58785000 {
+			compatible = "socionext,uniphier-fi2c";
+			reg = <0x58785000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 25 4>;
+			clocks = <&peri_clk 9>;
+			clock-frequency = <400000>;
+		};
 
-	/* chip-internal connection for HDMI */
-	i2c6: i2c at 58786000 {
-		compatible = "socionext,uniphier-fi2c";
-		reg = <0x58786000 0x80>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 26 4>;
-		clocks = <&i2c_clk>;
-		clock-frequency = <400000>;
-	};
+		/* chip-internal connection for HDMI */
+		i2c6: i2c at 58786000 {
+			compatible = "socionext,uniphier-fi2c";
+			reg = <0x58786000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 26 4>;
+			clocks = <&peri_clk 10>;
+			clock-frequency = <400000>;
+		};
 
-	sd: sdhc at 5a400000 {
-		compatible = "socionext,uniphier-sdhc";
-		status = "disabled";
-		reg = <0x5a400000 0x200>;
-		interrupts = <0 76 4>;
-		pinctrl-names = "default", "1.8v";
-		pinctrl-0 = <&pinctrl_sd>;
-		pinctrl-1 = <&pinctrl_sd_1v8>;
-		clocks = <&mio_clk 0>;
-		reset-names = "host", "bridge";
-		resets = <&mio_rst 0>, <&mio_rst 3>;
-		bus-width = <4>;
-	};
+		system_bus: system-bus at 58c00000 {
+			compatible = "socionext,uniphier-system-bus";
+			status = "disabled";
+			reg = <0x58c00000 0x400>;
+			#address-cells = <2>;
+			#size-cells = <1>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_system_bus>;
+		};
 
-	emmc: sdhc at 5a500000 {
-		compatible = "socionext,uniphier-sdhc";
-		status = "disabled";
-		reg = <0x5a500000 0x200>;
-		interrupts = <0 78 4>;
-		pinctrl-names = "default", "1.8v";
-		pinctrl-0 = <&pinctrl_emmc>;
-		pinctrl-1 = <&pinctrl_emmc_1v8>;
-		clocks = <&mio_clk 1>;
-		reset-names = "host", "bridge", "hw-reset";
-		resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
-		bus-width = <8>;
-		non-removable;
-	};
+		smpctrl at 59800000 {
+			compatible = "socionext,uniphier-smpctrl";
+			reg = <0x59801000 0x400>;
+		};
 
-	sd1: sdhc at 5a600000 {
-		compatible = "socionext,uniphier-sdhc";
-		status = "disabled";
-		reg = <0x5a600000 0x200>;
-		interrupts = <0 85 4>;
-		pinctrl-names = "default", "1.8v";
-		pinctrl-0 = <&pinctrl_sd1>;
-		pinctrl-1 = <&pinctrl_sd1_1v8>;
-		clocks = <&mio_clk 2>;
-		resets = <&mio_rst 2>, <&mio_rst 5>;
-		bus-width = <4>;
-	};
+		mioctrl at 59810000 {
+			compatible = "socionext,uniphier-pro4-mioctrl",
+				     "simple-mfd", "syscon";
+			reg = <0x59810000 0x800>;
+			u-boot,dm-pre-reloc;
+
+			mio_clk: clock {
+				compatible = "socionext,uniphier-pro4-mio-clock";
+				#clock-cells = <1>;
+			};
+
+			mio_rst: reset {
+				compatible = "socionext,uniphier-pro4-mio-reset";
+				#reset-cells = <1>;
+			};
+		};
 
-	usb2: usb at 5a800100 {
-		compatible = "socionext,uniphier-ehci", "generic-ehci";
-		status = "disabled";
-		reg = <0x5a800100 0x100>;
-		interrupts = <0 80 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_usb2>;
-		clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
-		resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
-			 <&mio_rst 12>;
-	};
+		perictrl at 59820000 {
+			compatible = "socionext,uniphier-pro4-perictrl",
+				     "simple-mfd", "syscon";
+			reg = <0x59820000 0x200>;
 
-	usb3: usb at 5a810100 {
-		compatible = "socionext,uniphier-ehci", "generic-ehci";
-		status = "disabled";
-		reg = <0x5a810100 0x100>;
-		interrupts = <0 81 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_usb3>;
-		clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
-		resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
-			 <&mio_rst 13>;
-	};
+			peri_clk: clock {
+				compatible = "socionext,uniphier-pro4-peri-clock";
+				#clock-cells = <1>;
+			};
 
-	aidet at 5fc20000 {
-		compatible = "simple-mfd", "syscon";
-		reg = <0x5fc20000 0x200>;
-	};
+			peri_rst: reset {
+				compatible = "socionext,uniphier-pro4-peri-reset";
+				#reset-cells = <1>;
+			};
+		};
 
-	usb0: usb at 65a00000 {
-		compatible = "socionext,uniphier-xhci", "generic-xhci";
-		status = "disabled";
-		reg = <0x65a00000 0x100>;
-		interrupts = <0 134 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_usb0>;
-	};
+		sd: sdhc at 5a400000 {
+			compatible = "socionext,uniphier-sdhc";
+			status = "disabled";
+			reg = <0x5a400000 0x200>;
+			interrupts = <0 76 4>;
+			pinctrl-names = "default", "1.8v";
+			pinctrl-0 = <&pinctrl_sd>;
+			pinctrl-1 = <&pinctrl_sd_1v8>;
+			clocks = <&mio_clk 0>;
+			reset-names = "host", "bridge";
+			resets = <&mio_rst 0>, <&mio_rst 3>;
+			bus-width = <4>;
+			cap-sd-highspeed;
+			sd-uhs-sdr12;
+			sd-uhs-sdr25;
+			sd-uhs-sdr50;
+		};
 
-	usb1: usb at 65c00000 {
-		compatible = "socionext,uniphier-xhci", "generic-xhci";
-		status = "disabled";
-		reg = <0x65c00000 0x100>;
-		interrupts = <0 137 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_usb1>;
-	};
-};
+		emmc: sdhc at 5a500000 {
+			compatible = "socionext,uniphier-sdhc";
+			status = "disabled";
+			reg = <0x5a500000 0x200>;
+			interrupts = <0 78 4>;
+			pinctrl-names = "default", "1.8v";
+			pinctrl-0 = <&pinctrl_emmc>;
+			pinctrl-1 = <&pinctrl_emmc_1v8>;
+			clocks = <&mio_clk 1>;
+			reset-names = "host", "bridge";
+			resets = <&mio_rst 1>, <&mio_rst 4>;
+			bus-width = <8>;
+			non-removable;
+			cap-mmc-highspeed;
+			cap-mmc-hw-reset;
+		};
 
-&refclk {
-	clock-frequency = <25000000>;
-};
+		sd1: sdhc at 5a600000 {
+			compatible = "socionext,uniphier-sdhc";
+			status = "disabled";
+			reg = <0x5a600000 0x200>;
+			interrupts = <0 85 4>;
+			pinctrl-names = "default", "1.8v";
+			pinctrl-0 = <&pinctrl_sd1>;
+			pinctrl-1 = <&pinctrl_sd1_1v8>;
+			clocks = <&mio_clk 2>;
+			resets = <&mio_rst 2>, <&mio_rst 5>;
+			bus-width = <4>;
+			cap-sd-highspeed;
+			sd-uhs-sdr12;
+			sd-uhs-sdr25;
+			sd-uhs-sdr50;
+		};
 
-&serial0 {
-	clock-frequency = <73728000>;
-};
+		usb2: usb at 5a800100 {
+			compatible = "socionext,uniphier-ehci", "generic-ehci";
+			status = "disabled";
+			reg = <0x5a800100 0x100>;
+			interrupts = <0 80 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb2>;
+			clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
+			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
+				 <&mio_rst 12>;
+		};
 
-&serial1 {
-	clock-frequency = <73728000>;
-};
+		usb3: usb at 5a810100 {
+			compatible = "socionext,uniphier-ehci", "generic-ehci";
+			status = "disabled";
+			reg = <0x5a810100 0x100>;
+			interrupts = <0 81 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb3>;
+			clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
+			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
+				 <&mio_rst 13>;
+		};
 
-&serial2 {
-	clock-frequency = <73728000>;
-};
+		soc-glue at 5f800000 {
+			compatible = "socionext,uniphier-pro4-soc-glue",
+				     "simple-mfd", "syscon";
+			reg = <0x5f800000 0x2000>;
+			u-boot,dm-pre-reloc;
 
-&serial3 {
-	clock-frequency = <73728000>;
-};
+			pinctrl: pinctrl {
+				compatible = "socionext,uniphier-pro4-pinctrl";
+				u-boot,dm-pre-reloc;
+			};
+		};
 
-&mio_clk {
-	compatible = "socionext,uniphier-pro4-mio-clock";
-};
+		aidet at 5fc20000 {
+			compatible = "simple-mfd", "syscon";
+			reg = <0x5fc20000 0x200>;
+		};
 
-&mio_rst {
-	compatible = "socionext,uniphier-pro4-mio-reset";
-};
+		timer at 60000200 {
+			compatible = "arm,cortex-a9-global-timer";
+			reg = <0x60000200 0x20>;
+			interrupts = <1 11 0x304>;
+			clocks = <&arm_timer_clk>;
+		};
 
-&peri_clk {
-	compatible = "socionext,uniphier-pro4-peri-clock";
-};
+		timer at 60000600 {
+			compatible = "arm,cortex-a9-twd-timer";
+			reg = <0x60000600 0x20>;
+			interrupts = <1 13 0x304>;
+			clocks = <&arm_timer_clk>;
+		};
 
-&peri_rst {
-	compatible = "socionext,uniphier-pro4-peri-reset";
-};
+		intc: interrupt-controller at 60001000 {
+			compatible = "arm,cortex-a9-gic";
+			reg = <0x60001000 0x1000>,
+			      <0x60000100 0x100>;
+			#interrupt-cells = <3>;
+			interrupt-controller;
+		};
 
-&pinctrl {
-	compatible = "socionext,uniphier-pro4-pinctrl";
-};
+		sysctrl at 61840000 {
+			compatible = "socionext,uniphier-pro4-sysctrl",
+				     "simple-mfd", "syscon";
+			reg = <0x61840000 0x10000>;
 
-&sys_clk {
-	compatible = "socionext,uniphier-pro4-clock";
-};
+			sys_clk: clock {
+				compatible = "socionext,uniphier-pro4-clock";
+				#clock-cells = <1>;
+			};
 
-&sys_rst {
-	compatible = "socionext,uniphier-pro4-reset";
+			sys_rst: reset {
+				compatible = "socionext,uniphier-pro4-reset";
+				#reset-cells = <1>;
+			};
+		};
+
+		usb0: usb at 65b00000 {
+			compatible = "socionext,uniphier-pro4-dwc3";
+			status = "disabled";
+			reg = <0x65b00000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb0>;
+			dwc3 at 65a00000 {
+				compatible = "snps,dwc3";
+				reg = <0x65a00000 0x10000>;
+				interrupts = <0 134 4>;
+				tx-fifo-resize;
+			};
+		};
+
+		usb1: usb at 65d00000 {
+			compatible = "socionext,uniphier-pro4-dwc3";
+			status = "disabled";
+			reg = <0x65d00000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb1>;
+			dwc3 at 65c00000 {
+				compatible = "snps,dwc3";
+				reg = <0x65c00000 0x10000>;
+				interrupts = <0 137 4>;
+				tx-fifo-resize;
+			};
+		};
+
+		nand: nand at 68000000 {
+			compatible = "socionext,denali-nand-v5a";
+			status = "disabled";
+			reg-names = "nand_data", "denali_reg";
+			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+			interrupts = <0 65 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_nand>;
+			clocks = <&sys_clk 2>;
+			nand-ecc-strength = <8>;
+		};
+	};
 };
+
+/include/ "uniphier-pinctrl.dtsi"
diff --git a/arch/arm/dts/uniphier-pro5.dtsi b/arch/arm/dts/uniphier-pro5.dtsi
index 97edc89..68866e1 100644
--- a/arch/arm/dts/uniphier-pro5.dtsi
+++ b/arch/arm/dts/uniphier-pro5.dtsi
@@ -7,7 +7,7 @@
  * SPDX-License-Identifier:	GPL-2.0+	X11
  */
 
-/include/ "uniphier-common32.dtsi"
+/include/ "skeleton.dtsi"
 
 / {
 	compatible = "socionext,uniphier-pro5";
@@ -20,433 +20,652 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <0>;
+			clocks = <&sys_clk 32>;
 			enable-method = "psci";
 			next-level-cache = <&l2>;
+			operating-points-v2 = <&cpu_opp>;
 		};
 
 		cpu at 1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <1>;
+			clocks = <&sys_clk 32>;
 			enable-method = "psci";
 			next-level-cache = <&l2>;
+			operating-points-v2 = <&cpu_opp>;
 		};
 	};
 
+	cpu_opp: opp_table {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp at 100000000 {
+			opp-hz = /bits/ 64 <100000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 116667000 {
+			opp-hz = /bits/ 64 <116667000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 150000000 {
+			opp-hz = /bits/ 64 <150000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 175000000 {
+			opp-hz = /bits/ 64 <175000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 200000000 {
+			opp-hz = /bits/ 64 <200000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 233334000 {
+			opp-hz = /bits/ 64 <233334000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 300000000 {
+			opp-hz = /bits/ 64 <300000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 350000000 {
+			opp-hz = /bits/ 64 <350000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 400000000 {
+			opp-hz = /bits/ 64 <400000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 466667000 {
+			opp-hz = /bits/ 64 <466667000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 700000000 {
+			opp-hz = /bits/ 64 <700000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 800000000 {
+			opp-hz = /bits/ 64 <800000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 933334000 {
+			opp-hz = /bits/ 64 <933334000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 1200000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 1400000000 {
+			opp-hz = /bits/ 64 <1400000000>;
+			clock-latency-ns = <300>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
 	clocks {
-		arm_timer_clk: arm_timer_clk {
-			#clock-cells = <0>;
+		refclk: ref {
 			compatible = "fixed-clock";
-			clock-frequency = <50000000>;
+			#clock-cells = <0>;
+			clock-frequency = <20000000>;
 		};
 
-		i2c_clk: i2c_clk {
+		arm_timer_clk: arm_timer_clk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <50000000>;
 		};
 	};
-};
 
-&soc {
-	l2: l2-cache at 500c0000 {
-		compatible = "socionext,uniphier-system-cache";
-		reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>;
-		interrupts = <0 190 4>, <0 191 4>;
-		cache-unified;
-		cache-size = <(2 * 1024 * 1024)>;
-		cache-sets = <512>;
-		cache-line-size = <128>;
-		cache-level = <2>;
-		next-level-cache = <&l3>;
-	};
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		interrupt-parent = <&intc>;
+		u-boot,dm-pre-reloc;
+
+		l2: l2-cache at 500c0000 {
+			compatible = "socionext,uniphier-system-cache";
+			reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
+			      <0x506c0000 0x400>;
+			interrupts = <0 190 4>, <0 191 4>;
+			cache-unified;
+			cache-size = <(2 * 1024 * 1024)>;
+			cache-sets = <512>;
+			cache-line-size = <128>;
+			cache-level = <2>;
+			next-level-cache = <&l3>;
+		};
 
-	l3: l3-cache at 500c8000 {
-		compatible = "socionext,uniphier-system-cache";
-		reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>;
-		interrupts = <0 174 4>, <0 175 4>;
-		cache-unified;
-		cache-size = <(2 * 1024 * 1024)>;
-		cache-sets = <512>;
-		cache-line-size = <256>;
-		cache-level = <3>;
-	};
+		l3: l3-cache at 500c8000 {
+			compatible = "socionext,uniphier-system-cache";
+			reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
+			      <0x506c8000 0x400>;
+			interrupts = <0 174 4>, <0 175 4>;
+			cache-unified;
+			cache-size = <(2 * 1024 * 1024)>;
+			cache-sets = <512>;
+			cache-line-size = <256>;
+			cache-level = <3>;
+		};
 
-	port0x: gpio at 55000008 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000008 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		serial0: serial at 54006800 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006800 0x40>;
+			interrupts = <0 33 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart0>;
+			clocks = <&peri_clk 0>;
+			clock-frequency = <73728000>;
+		};
 
-	port1x: gpio at 55000010 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000010 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		serial1: serial at 54006900 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006900 0x40>;
+			interrupts = <0 35 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart1>;
+			clocks = <&peri_clk 1>;
+			clock-frequency = <73728000>;
+		};
 
-	port2x: gpio at 55000018 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000018 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		serial2: serial at 54006a00 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006a00 0x40>;
+			interrupts = <0 37 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart2>;
+			clocks = <&peri_clk 2>;
+			clock-frequency = <73728000>;
+		};
 
-	port3x: gpio at 55000020 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000020 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		serial3: serial at 54006b00 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006b00 0x40>;
+			interrupts = <0 177 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart3>;
+			clocks = <&peri_clk 3>;
+			clock-frequency = <73728000>;
+		};
 
-	port4: gpio at 55000028 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000028 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port0x: gpio at 55000008 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000008 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port5x: gpio at 55000030 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000030 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port1x: gpio at 55000010 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000010 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port6x: gpio at 55000038 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000038 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port2x: gpio at 55000018 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000018 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port7x: gpio at 55000040 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000040 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port3x: gpio at 55000020 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000020 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port8x: gpio at 55000048 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000048 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port4: gpio at 55000028 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000028 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port9x: gpio at 55000050 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000050 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port5x: gpio at 55000030 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000030 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port10x: gpio at 55000058 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000058 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port6x: gpio at 55000038 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000038 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port11x: gpio at 55000060 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000060 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port7x: gpio at 55000040 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000040 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port12x: gpio at 55000068 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000068 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port8x: gpio at 55000048 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000048 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port13x: gpio at 55000070 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000070 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port9x: gpio at 55000050 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000050 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port14x: gpio at 55000078 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000078 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port10x: gpio at 55000058 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000058 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port17x: gpio at 550000a0 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000a0 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port11x: gpio at 55000060 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000060 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port18x: gpio at 550000a8 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000a8 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port12x: gpio at 55000068 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000068 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port19x: gpio at 550000b0 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000b0 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port13x: gpio at 55000070 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000070 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port20x: gpio at 550000b8 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000b8 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port14x: gpio at 55000078 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000078 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port21x: gpio at 550000c0 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000c0 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port17x: gpio at 550000a0 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000a0 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port22x: gpio at 550000c8 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000c8 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port18x: gpio at 550000a8 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000a8 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port23x: gpio at 550000d0 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000d0 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port19x: gpio at 550000b0 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000b0 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port24x: gpio at 550000d8 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000d8 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port20x: gpio at 550000b8 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000b8 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port25x: gpio at 550000e0 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000e0 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port21x: gpio at 550000c0 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000c0 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port26x: gpio at 550000e8 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000e8 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port22x: gpio at 550000c8 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000c8 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port27x: gpio at 550000f0 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000f0 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port23x: gpio at 550000d0 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000d0 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port28x: gpio at 550000f8 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000f8 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port24x: gpio at 550000d8 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000d8 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port29x: gpio at 55000100 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000100 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port25x: gpio at 550000e0 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000e0 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port30x: gpio at 55000108 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000108 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port26x: gpio at 550000e8 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000e8 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	i2c0: i2c at 58780000 {
-		compatible = "socionext,uniphier-fi2c";
-		status = "disabled";
-		reg = <0x58780000 0x80>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 41 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c0>;
-		clocks = <&i2c_clk>;
-		clock-frequency = <100000>;
-	};
+		port27x: gpio at 550000f0 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000f0 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	i2c1: i2c at 58781000 {
-		compatible = "socionext,uniphier-fi2c";
-		status = "disabled";
-		reg = <0x58781000 0x80>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 42 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c1>;
-		clocks = <&i2c_clk>;
-		clock-frequency = <100000>;
-	};
+		port28x: gpio at 550000f8 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000f8 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	i2c2: i2c at 58782000 {
-		compatible = "socionext,uniphier-fi2c";
-		status = "disabled";
-		reg = <0x58782000 0x80>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 43 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c2>;
-		clocks = <&i2c_clk>;
-		clock-frequency = <100000>;
-	};
+		port29x: gpio at 55000100 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000100 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	i2c3: i2c at 58783000 {
-		compatible = "socionext,uniphier-fi2c";
-		status = "disabled";
-		reg = <0x58783000 0x80>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 44 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c3>;
-		clocks = <&i2c_clk>;
-		clock-frequency = <100000>;
-	};
+		port30x: gpio at 55000108 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000108 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	/* i2c4 does not exist */
+		i2c0: i2c at 58780000 {
+			compatible = "socionext,uniphier-fi2c";
+			status = "disabled";
+			reg = <0x58780000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 41 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c0>;
+			clocks = <&peri_clk 4>;
+			clock-frequency = <100000>;
+		};
 
-	/* chip-internal connection for DMD */
-	i2c5: i2c at 58785000 {
-		compatible = "socionext,uniphier-fi2c";
-		reg = <0x58785000 0x80>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 25 4>;
-		clocks = <&i2c_clk>;
-		clock-frequency = <400000>;
-	};
+		i2c1: i2c at 58781000 {
+			compatible = "socionext,uniphier-fi2c";
+			status = "disabled";
+			reg = <0x58781000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 42 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c1>;
+			clocks = <&peri_clk 5>;
+			clock-frequency = <100000>;
+		};
 
-	/* chip-internal connection for HDMI */
-	i2c6: i2c at 58786000 {
-		compatible = "socionext,uniphier-fi2c";
-		reg = <0x58786000 0x80>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 26 4>;
-		clocks = <&i2c_clk>;
-		clock-frequency = <400000>;
-	};
+		i2c2: i2c at 58782000 {
+			compatible = "socionext,uniphier-fi2c";
+			status = "disabled";
+			reg = <0x58782000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 43 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c2>;
+			clocks = <&peri_clk 6>;
+			clock-frequency = <100000>;
+		};
 
-	aidet at 5fc20000 {
-		compatible = "simple-mfd", "syscon";
-		reg = <0x5fc20000 0x200>;
-	};
+		i2c3: i2c at 58783000 {
+			compatible = "socionext,uniphier-fi2c";
+			status = "disabled";
+			reg = <0x58783000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 44 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c3>;
+			clocks = <&peri_clk 7>;
+			clock-frequency = <100000>;
+		};
 
-	emmc: sdhc at 68400000 {
-		compatible = "socionext,uniphier-sdhc";
-		status = "disabled";
-		reg = <0x68400000 0x800>;
-		interrupts = <0 78 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_emmc>;
-		clocks = <&mio_clk 1>;
-		reset-names = "host", "hw-reset";
-		resets = <&mio_rst 1>, <&mio_rst 6>;
-		bus-width = <8>;
-		non-removable;
-	};
+		/* i2c4 does not exist */
+
+		/* chip-internal connection for DMD */
+		i2c5: i2c at 58785000 {
+			compatible = "socionext,uniphier-fi2c";
+			reg = <0x58785000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 25 4>;
+			clocks = <&peri_clk 9>;
+			clock-frequency = <400000>;
+		};
 
-	sd: sdhc at 68800000 {
-		compatible = "socionext,uniphier-sdhc";
-		status = "disabled";
-		reg = <0x68800000 0x800>;
-		interrupts = <0 76 4>;
-		pinctrl-names = "default", "1.8v";
-		pinctrl-0 = <&pinctrl_sd>;
-		pinctrl-1 = <&pinctrl_sd_1v8>;
-		clocks = <&mio_clk 0>;
-		reset-names = "host";
-		resets = <&mio_rst 0>;
-		bus-width = <4>;
-	};
+		/* chip-internal connection for HDMI */
+		i2c6: i2c at 58786000 {
+			compatible = "socionext,uniphier-fi2c";
+			reg = <0x58786000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 26 4>;
+			clocks = <&peri_clk 10>;
+			clock-frequency = <400000>;
+		};
 
-	usb0: usb at 65a00000 {
-		compatible = "socionext,uniphier-xhci", "generic-xhci";
-		status = "disabled";
-		reg = <0x65a00000 0x100>;
-		interrupts = <0 134 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_usb0>;
-	};
+		system_bus: system-bus at 58c00000 {
+			compatible = "socionext,uniphier-system-bus";
+			status = "disabled";
+			reg = <0x58c00000 0x400>;
+			#address-cells = <2>;
+			#size-cells = <1>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_system_bus>;
+		};
 
-	usb1: usb at 65c00000 {
-		compatible = "socionext,uniphier-xhci", "generic-xhci";
-		status = "disabled";
-		reg = <0x65c00000 0x100>;
-		interrupts = <0 137 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
-	};
-};
+		smpctrl at 59800000 {
+			compatible = "socionext,uniphier-smpctrl";
+			reg = <0x59801000 0x400>;
+		};
 
-&refclk {
-	clock-frequency = <20000000>;
-};
+		sdctrl at 59810000 {
+			compatible = "socionext,uniphier-pro5-sdctrl",
+				     "simple-mfd", "syscon";
+			reg = <0x59810000 0x800>;
+			u-boot,dm-pre-reloc;
+
+			sd_clk: clock {
+				compatible = "socionext,uniphier-pro5-sd-clock";
+				#clock-cells = <1>;
+			};
+
+			sd_rst: reset {
+				compatible = "socionext,uniphier-pro5-sd-reset";
+				#reset-cells = <1>;
+			};
+		};
 
-&serial0 {
-	clock-frequency = <73728000>;
-};
+		perictrl at 59820000 {
+			compatible = "socionext,uniphier-pro5-perictrl",
+				     "simple-mfd", "syscon";
+			reg = <0x59820000 0x200>;
 
-&serial1 {
-	clock-frequency = <73728000>;
-};
+			peri_clk: clock {
+				compatible = "socionext,uniphier-pro5-peri-clock";
+				#clock-cells = <1>;
+			};
 
-&serial2 {
-	clock-frequency = <73728000>;
-};
+			peri_rst: reset {
+				compatible = "socionext,uniphier-pro5-peri-reset";
+				#reset-cells = <1>;
+			};
+		};
 
-&serial3 {
-	clock-frequency = <73728000>;
-};
+		soc-glue at 5f800000 {
+			compatible = "socionext,uniphier-pro5-soc-glue",
+				     "simple-mfd", "syscon";
+			reg = <0x5f800000 0x2000>;
+			u-boot,dm-pre-reloc;
 
-&mio_clk {
-	compatible = "socionext,uniphier-pro5-mio-clock";
-};
+			pinctrl: pinctrl {
+				compatible = "socionext,uniphier-pro5-pinctrl";
+				u-boot,dm-pre-reloc;
+			};
+		};
 
-&mio_rst {
-	compatible = "socionext,uniphier-pro5-mio-reset";
-};
+		aidet at 5fc20000 {
+			compatible = "simple-mfd", "syscon";
+			reg = <0x5fc20000 0x200>;
+		};
 
-&peri_clk {
-	compatible = "socionext,uniphier-pro5-peri-clock";
-};
+		timer at 60000200 {
+			compatible = "arm,cortex-a9-global-timer";
+			reg = <0x60000200 0x20>;
+			interrupts = <1 11 0x304>;
+			clocks = <&arm_timer_clk>;
+		};
 
-&peri_rst {
-	compatible = "socionext,uniphier-pro5-peri-reset";
-};
+		timer at 60000600 {
+			compatible = "arm,cortex-a9-twd-timer";
+			reg = <0x60000600 0x20>;
+			interrupts = <1 13 0x304>;
+			clocks = <&arm_timer_clk>;
+		};
 
-&pinctrl {
-	compatible = "socionext,uniphier-pro5-pinctrl";
-};
+		intc: interrupt-controller at 60001000 {
+			compatible = "arm,cortex-a9-gic";
+			reg = <0x60001000 0x1000>,
+			      <0x60000100 0x100>;
+			#interrupt-cells = <3>;
+			interrupt-controller;
+		};
 
-&sys_clk {
-	compatible = "socionext,uniphier-pro5-clock";
-};
+		sysctrl at 61840000 {
+			compatible = "socionext,uniphier-pro5-sysctrl",
+				     "simple-mfd", "syscon";
+			reg = <0x61840000 0x10000>;
+
+			sys_clk: clock {
+				compatible = "socionext,uniphier-pro5-clock";
+				#clock-cells = <1>;
+			};
+
+			sys_rst: reset {
+				compatible = "socionext,uniphier-pro5-reset";
+				#reset-cells = <1>;
+			};
+		};
+
+		usb0: usb at 65b00000 {
+			compatible = "socionext,uniphier-pro5-dwc3";
+			status = "disabled";
+			reg = <0x65b00000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb0>;
+			dwc3 at 65a00000 {
+				compatible = "snps,dwc3";
+				reg = <0x65a00000 0x10000>;
+				interrupts = <0 134 4>;
+				tx-fifo-resize;
+			};
+		};
 
-&sys_rst {
-	compatible = "socionext,uniphier-pro5-reset";
+		usb1: usb at 65d00000 {
+			compatible = "socionext,uniphier-pro5-dwc3";
+			status = "disabled";
+			reg = <0x65d00000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
+			dwc3 at 65c00000 {
+				compatible = "snps,dwc3";
+				reg = <0x65c00000 0x10000>;
+				interrupts = <0 137 4>;
+				tx-fifo-resize;
+			};
+		};
+
+		nand: nand at 68000000 {
+			compatible = "socionext,denali-nand-v5b";
+			status = "disabled";
+			reg-names = "nand_data", "denali_reg";
+			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+			interrupts = <0 65 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_nand>;
+			clocks = <&sys_clk 2>;
+			nand-ecc-strength = <8>;
+		};
+
+		emmc: sdhc at 68400000 {
+			compatible = "socionext,uniphier-sdhc";
+			status = "disabled";
+			reg = <0x68400000 0x800>;
+			interrupts = <0 78 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_emmc>;
+			clocks = <&sd_clk 1>;
+			reset-names = "host";
+			resets = <&sd_rst 1>;
+			bus-width = <8>;
+			non-removable;
+			cap-mmc-highspeed;
+			cap-mmc-hw-reset;
+			no-3-3-v;
+		};
+
+		sd: sdhc at 68800000 {
+			compatible = "socionext,uniphier-sdhc";
+			status = "disabled";
+			reg = <0x68800000 0x800>;
+			interrupts = <0 76 4>;
+			pinctrl-names = "default", "1.8v";
+			pinctrl-0 = <&pinctrl_sd>;
+			pinctrl-1 = <&pinctrl_sd_1v8>;
+			clocks = <&sd_clk 0>;
+			reset-names = "host";
+			resets = <&sd_rst 0>;
+			bus-width = <4>;
+			cap-sd-highspeed;
+			sd-uhs-sdr12;
+			sd-uhs-sdr25;
+			sd-uhs-sdr50;
+		};
+	};
 };
+
+/include/ "uniphier-pinctrl.dtsi"
diff --git a/arch/arm/dts/uniphier-pxs2-gentil.dts b/arch/arm/dts/uniphier-pxs2-gentil.dts
index a98e758..0a6d46c 100644
--- a/arch/arm/dts/uniphier-pxs2-gentil.dts
+++ b/arch/arm/dts/uniphier-pxs2-gentil.dts
@@ -71,7 +71,7 @@
 	u-boot,dm-pre-reloc;
 };
 
-&mio_clk {
+&sd_clk {
 	u-boot,dm-pre-reloc;
 };
 
diff --git a/arch/arm/dts/uniphier-pxs2-vodka.dts b/arch/arm/dts/uniphier-pxs2-vodka.dts
index 78a52a8..770edca 100644
--- a/arch/arm/dts/uniphier-pxs2-vodka.dts
+++ b/arch/arm/dts/uniphier-pxs2-vodka.dts
@@ -55,7 +55,7 @@
 	u-boot,dm-pre-reloc;
 };
 
-&mio_clk {
+&sd_clk {
 	u-boot,dm-pre-reloc;
 };
 
diff --git a/arch/arm/dts/uniphier-pxs2.dtsi b/arch/arm/dts/uniphier-pxs2.dtsi
index b64107b..da62070 100644
--- a/arch/arm/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/dts/uniphier-pxs2.dtsi
@@ -7,7 +7,7 @@
  * SPDX-License-Identifier:	GPL-2.0+	X11
  */
 
-/include/ "uniphier-common32.dtsi"
+/include/ "skeleton.dtsi"
 
 / {
 	compatible = "socionext,uniphier-pxs2";
@@ -20,36 +20,93 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <0>;
+			clocks = <&sys_clk 32>;
 			enable-method = "psci";
 			next-level-cache = <&l2>;
+			operating-points-v2 = <&cpu_opp>;
 		};
 
 		cpu at 1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <1>;
+			clocks = <&sys_clk 32>;
 			enable-method = "psci";
 			next-level-cache = <&l2>;
+			operating-points-v2 = <&cpu_opp>;
 		};
 
 		cpu at 2 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <2>;
+			clocks = <&sys_clk 32>;
 			enable-method = "psci";
 			next-level-cache = <&l2>;
+			operating-points-v2 = <&cpu_opp>;
 		};
 
 		cpu at 3 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <3>;
+			clocks = <&sys_clk 32>;
 			enable-method = "psci";
 			next-level-cache = <&l2>;
+			operating-points-v2 = <&cpu_opp>;
 		};
 	};
 
+	cpu_opp: opp_table {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp at 100000000 {
+			opp-hz = /bits/ 64 <100000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 150000000 {
+			opp-hz = /bits/ 64 <150000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 200000000 {
+			opp-hz = /bits/ 64 <200000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 300000000 {
+			opp-hz = /bits/ 64 <300000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 400000000 {
+			opp-hz = /bits/ 64 <400000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 800000000 {
+			opp-hz = /bits/ 64 <800000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 1200000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			clock-latency-ns = <300>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
 	clocks {
+		refclk: ref {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <25000000>;
+		};
+
 		arm_timer_clk: arm_timer_clk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
@@ -62,397 +119,536 @@
 			clock-frequency = <50000000>;
 		};
 	};
-};
 
-&soc {
-	l2: l2-cache at 500c0000 {
-		compatible = "socionext,uniphier-system-cache";
-		reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
-		interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
-		cache-unified;
-		cache-size = <(1280 * 1024)>;
-		cache-sets = <512>;
-		cache-line-size = <128>;
-		cache-level = <2>;
-	};
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		interrupt-parent = <&intc>;
+		u-boot,dm-pre-reloc;
+
+		l2: l2-cache at 500c0000 {
+			compatible = "socionext,uniphier-system-cache";
+			reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
+			      <0x506c0000 0x400>;
+			interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
+			cache-unified;
+			cache-size = <(1280 * 1024)>;
+			cache-sets = <512>;
+			cache-line-size = <128>;
+			cache-level = <2>;
+		};
 
-	port0x: gpio at 55000008 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000008 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		serial0: serial at 54006800 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006800 0x40>;
+			interrupts = <0 33 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart0>;
+			clocks = <&peri_clk 0>;
+			clock-frequency = <88900000>;
+		};
 
-	port1x: gpio at 55000010 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000010 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		serial1: serial at 54006900 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006900 0x40>;
+			interrupts = <0 35 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart1>;
+			clocks = <&peri_clk 1>;
+			clock-frequency = <88900000>;
+		};
 
-	port2x: gpio at 55000018 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000018 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		serial2: serial at 54006a00 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006a00 0x40>;
+			interrupts = <0 37 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart2>;
+			clocks = <&peri_clk 2>;
+			clock-frequency = <88900000>;
+		};
 
-	port3x: gpio at 55000020 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000020 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		serial3: serial at 54006b00 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006b00 0x40>;
+			interrupts = <0 177 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart3>;
+			clocks = <&peri_clk 3>;
+			clock-frequency = <88900000>;
+		};
 
-	port4: gpio at 55000028 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000028 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port0x: gpio at 55000008 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000008 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port5x: gpio at 55000030 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000030 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port1x: gpio at 55000010 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000010 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port6x: gpio at 55000038 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000038 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port2x: gpio at 55000018 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000018 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port7x: gpio at 55000040 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000040 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port3x: gpio at 55000020 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000020 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port8x: gpio at 55000048 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000048 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port4: gpio at 55000028 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000028 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port9x: gpio at 55000050 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000050 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port5x: gpio at 55000030 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000030 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port10x: gpio at 55000058 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000058 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port6x: gpio at 55000038 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000038 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port12x: gpio at 55000068 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000068 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port7x: gpio at 55000040 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000040 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port13x: gpio at 55000070 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000070 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port8x: gpio at 55000048 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000048 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port14x: gpio at 55000078 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000078 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port9x: gpio at 55000050 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000050 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port15x: gpio at 55000080 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000080 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port10x: gpio at 55000058 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000058 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port16x: gpio at 55000088 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000088 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port12x: gpio at 55000068 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000068 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port17x: gpio at 550000a0 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000a0 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port13x: gpio at 55000070 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000070 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port18x: gpio at 550000a8 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000a8 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port14x: gpio at 55000078 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000078 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port19x: gpio at 550000b0 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000b0 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port15x: gpio at 55000080 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000080 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port20x: gpio at 550000b8 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000b8 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port16x: gpio at 55000088 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000088 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port21x: gpio at 550000c0 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000c0 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port17x: gpio at 550000a0 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000a0 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port22x: gpio at 550000c8 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000c8 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port18x: gpio at 550000a8 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000a8 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port23x: gpio at 550000d0 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000d0 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port19x: gpio at 550000b0 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000b0 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port24x: gpio at 550000d8 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000d8 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port20x: gpio at 550000b8 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000b8 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port25x: gpio at 550000e0 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000e0 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port21x: gpio at 550000c0 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000c0 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port26x: gpio at 550000e8 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000e8 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port22x: gpio at 550000c8 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000c8 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port27x: gpio at 550000f0 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000f0 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port23x: gpio at 550000d0 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000d0 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port28x: gpio at 550000f8 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x550000f8 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port24x: gpio at 550000d8 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000d8 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	i2c0: i2c at 58780000 {
-		compatible = "socionext,uniphier-fi2c";
-		status = "disabled";
-		reg = <0x58780000 0x80>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 41 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c0>;
-		clocks = <&i2c_clk>;
-		clock-frequency = <100000>;
-	};
+		port25x: gpio at 550000e0 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000e0 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	i2c1: i2c at 58781000 {
-		compatible = "socionext,uniphier-fi2c";
-		status = "disabled";
-		reg = <0x58781000 0x80>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 42 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c1>;
-		clocks = <&i2c_clk>;
-		clock-frequency = <100000>;
-	};
+		port26x: gpio at 550000e8 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000e8 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	i2c2: i2c at 58782000 {
-		compatible = "socionext,uniphier-fi2c";
-		status = "disabled";
-		reg = <0x58782000 0x80>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c2>;
-		interrupts = <0 43 4>;
-		clocks = <&i2c_clk>;
-		clock-frequency = <100000>;
-	};
+		port27x: gpio at 550000f0 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000f0 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	i2c3: i2c at 58783000 {
-		compatible = "socionext,uniphier-fi2c";
-		status = "disabled";
-		reg = <0x58783000 0x80>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 44 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c3>;
-		clocks = <&i2c_clk>;
-		clock-frequency = <100000>;
-	};
+		port28x: gpio at 550000f8 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x550000f8 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	/* chip-internal connection for DMD */
-	i2c4: i2c at 58784000 {
-		compatible = "socionext,uniphier-fi2c";
-		reg = <0x58784000 0x80>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 45 4>;
-		clocks = <&i2c_clk>;
-		clock-frequency = <400000>;
-	};
+		i2c0: i2c at 58780000 {
+			compatible = "socionext,uniphier-fi2c";
+			status = "disabled";
+			reg = <0x58780000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 41 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c0>;
+			clocks = <&i2c_clk>;
+			clock-frequency = <100000>;
+		};
 
-	/* chip-internal connection for STM */
-	i2c5: i2c at 58785000 {
-		compatible = "socionext,uniphier-fi2c";
-		reg = <0x58785000 0x80>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 25 4>;
-		clocks = <&i2c_clk>;
-		clock-frequency = <400000>;
-	};
+		i2c1: i2c at 58781000 {
+			compatible = "socionext,uniphier-fi2c";
+			status = "disabled";
+			reg = <0x58781000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 42 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c1>;
+			clocks = <&i2c_clk>;
+			clock-frequency = <100000>;
+		};
 
-	/* chip-internal connection for HDMI */
-	i2c6: i2c at 58786000 {
-		compatible = "socionext,uniphier-fi2c";
-		reg = <0x58786000 0x80>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 26 4>;
-		clocks = <&i2c_clk>;
-		clock-frequency = <400000>;
-	};
+		i2c2: i2c at 58782000 {
+			compatible = "socionext,uniphier-fi2c";
+			status = "disabled";
+			reg = <0x58782000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 43 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c2>;
+			clocks = <&i2c_clk>;
+			clock-frequency = <100000>;
+		};
 
-	emmc: sdhc at 5a000000 {
-		compatible = "socionext,uniphier-sdhc";
-		status = "disabled";
-		reg = <0x5a000000 0x800>;
-		interrupts = <0 78 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_emmc>;
-		clocks = <&mio_clk 1>;
-		reset-names = "host", "hw-reset";
-		resets = <&mio_rst 1>, <&mio_rst 6>;
-		bus-width = <8>;
-		non-removable;
-	};
+		i2c3: i2c at 58783000 {
+			compatible = "socionext,uniphier-fi2c";
+			status = "disabled";
+			reg = <0x58783000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 44 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c3>;
+			clocks = <&i2c_clk>;
+			clock-frequency = <100000>;
+		};
 
-	sd: sdhc at 5a400000 {
-		compatible = "socionext,uniphier-sdhc";
-		status = "disabled";
-		reg = <0x5a400000 0x800>;
-		interrupts = <0 76 4>;
-		pinctrl-names = "default", "1.8v";
-		pinctrl-0 = <&pinctrl_sd>;
-		pinctrl-1 = <&pinctrl_sd_1v8>;
-		clocks = <&mio_clk 0>;
-		reset-names = "host";
-		resets = <&mio_rst 0>;
-		bus-width = <4>;
-	};
+		/* chip-internal connection for DMD */
+		i2c4: i2c at 58784000 {
+			compatible = "socionext,uniphier-fi2c";
+			reg = <0x58784000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 45 4>;
+			clocks = <&i2c_clk>;
+			clock-frequency = <400000>;
+		};
 
-	aidet at 5fc20000 {
-		compatible = "simple-mfd", "syscon";
-		reg = <0x5fc20000 0x200>;
-	};
+		/* chip-internal connection for STM */
+		i2c5: i2c at 58785000 {
+			compatible = "socionext,uniphier-fi2c";
+			reg = <0x58785000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 25 4>;
+			clocks = <&i2c_clk>;
+			clock-frequency = <400000>;
+		};
 
-	usb0: usb at 65a00000 {
-		compatible = "socionext,uniphier-xhci", "generic-xhci";
-		status = "disabled";
-		reg = <0x65a00000 0x100>;
-		interrupts = <0 134 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
-	};
+		/* chip-internal connection for HDMI */
+		i2c6: i2c at 58786000 {
+			compatible = "socionext,uniphier-fi2c";
+			reg = <0x58786000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 26 4>;
+			clocks = <&i2c_clk>;
+			clock-frequency = <400000>;
+		};
 
-	usb1: usb at 65c00000 {
-		compatible = "socionext,uniphier-xhci", "generic-xhci";
-		status = "disabled";
-		reg = <0x65c00000 0x100>;
-		interrupts = <0 137 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
-	};
-};
+		system_bus: system-bus at 58c00000 {
+			compatible = "socionext,uniphier-system-bus";
+			status = "disabled";
+			reg = <0x58c00000 0x400>;
+			#address-cells = <2>;
+			#size-cells = <1>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_system_bus>;
+		};
 
-&refclk {
-	clock-frequency = <25000000>;
-};
+		smpctrl at 59800000 {
+			compatible = "socionext,uniphier-smpctrl";
+			reg = <0x59801000 0x400>;
+		};
 
-&serial0 {
-	clock-frequency = <88900000>;
-};
+		sdctrl at 59810000 {
+			compatible = "socionext,uniphier-pxs2-sdctrl",
+				     "simple-mfd", "syscon";
+			reg = <0x59810000 0x800>;
+			u-boot,dm-pre-reloc;
+
+			sd_clk: clock {
+				compatible = "socionext,uniphier-pxs2-sd-clock";
+				#clock-cells = <1>;
+			};
+
+			sd_rst: reset {
+				compatible = "socionext,uniphier-pxs2-sd-reset";
+				#reset-cells = <1>;
+			};
+		};
 
-&serial1 {
-	clock-frequency = <88900000>;
-};
+		perictrl at 59820000 {
+			compatible = "socionext,uniphier-pxs2-perictrl",
+				     "simple-mfd", "syscon";
+			reg = <0x59820000 0x200>;
 
-&serial2 {
-	clock-frequency = <88900000>;
-};
+			peri_clk: clock {
+				compatible = "socionext,uniphier-pxs2-peri-clock";
+				#clock-cells = <1>;
+			};
 
-&serial3 {
-	clock-frequency = <88900000>;
-};
+			peri_rst: reset {
+				compatible = "socionext,uniphier-pxs2-peri-reset";
+				#reset-cells = <1>;
+			};
+		};
 
-&mio_clk {
-	compatible = "socionext,uniphier-pxs2-mio-clock";
-};
+		emmc: sdhc at 5a000000 {
+			compatible = "socionext,uniphier-sdhc";
+			status = "disabled";
+			reg = <0x5a000000 0x800>;
+			interrupts = <0 78 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_emmc>;
+			clocks = <&sd_clk 1>;
+			reset-names = "host";
+			resets = <&sd_rst 1>;
+			bus-width = <8>;
+			non-removable;
+			cap-mmc-highspeed;
+			cap-mmc-hw-reset;
+			no-3-3-v;
+		};
 
-&mio_rst {
-	compatible = "socionext,uniphier-pxs2-mio-reset";
-};
+		sd: sdhc at 5a400000 {
+			compatible = "socionext,uniphier-sdhc";
+			status = "disabled";
+			reg = <0x5a400000 0x800>;
+			interrupts = <0 76 4>;
+			pinctrl-names = "default", "1.8v";
+			pinctrl-0 = <&pinctrl_sd>;
+			pinctrl-1 = <&pinctrl_sd_1v8>;
+			clocks = <&sd_clk 0>;
+			reset-names = "host";
+			resets = <&sd_rst 0>;
+			bus-width = <4>;
+			cap-sd-highspeed;
+			sd-uhs-sdr12;
+			sd-uhs-sdr25;
+			sd-uhs-sdr50;
+		};
 
-&peri_clk {
-	compatible = "socionext,uniphier-pxs2-peri-clock";
-};
+		soc-glue at 5f800000 {
+			compatible = "socionext,uniphier-pxs2-soc-glue",
+				     "simple-mfd", "syscon";
+			reg = <0x5f800000 0x2000>;
+			u-boot,dm-pre-reloc;
 
-&peri_rst {
-	compatible = "socionext,uniphier-pxs2-peri-reset";
-};
+			pinctrl: pinctrl {
+				compatible = "socionext,uniphier-pxs2-pinctrl";
+				u-boot,dm-pre-reloc;
+			};
+		};
 
-&pinctrl {
-	compatible = "socionext,uniphier-pxs2-pinctrl";
-};
+		aidet at 5fc20000 {
+			compatible = "simple-mfd", "syscon";
+			reg = <0x5fc20000 0x200>;
+		};
 
-&sys_clk {
-	compatible = "socionext,uniphier-pxs2-clock";
-};
+		timer at 60000200 {
+			compatible = "arm,cortex-a9-global-timer";
+			reg = <0x60000200 0x20>;
+			interrupts = <1 11 0xf04>;
+			clocks = <&arm_timer_clk>;
+		};
+
+		timer at 60000600 {
+			compatible = "arm,cortex-a9-twd-timer";
+			reg = <0x60000600 0x20>;
+			interrupts = <1 13 0xf04>;
+			clocks = <&arm_timer_clk>;
+		};
+
+		intc: interrupt-controller at 60001000 {
+			compatible = "arm,cortex-a9-gic";
+			reg = <0x60001000 0x1000>,
+			      <0x60000100 0x100>;
+			#interrupt-cells = <3>;
+			interrupt-controller;
+		};
+
+		sysctrl at 61840000 {
+			compatible = "socionext,uniphier-pxs2-sysctrl",
+				     "simple-mfd", "syscon";
+			reg = <0x61840000 0x4000>;
+
+			sys_clk: clock {
+				compatible = "socionext,uniphier-pxs2-clock";
+				#clock-cells = <1>;
+			};
 
-&sys_rst {
-	compatible = "socionext,uniphier-pxs2-reset";
+			sys_rst: reset {
+				compatible = "socionext,uniphier-pxs2-reset";
+				#reset-cells = <1>;
+			};
+		};
+
+		usb0: usb at 65b00000 {
+			compatible = "socionext,uniphier-pxs2-dwc3";
+			status = "disabled";
+			reg = <0x65b00000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
+			dwc3 at 65a00000 {
+				compatible = "snps,dwc3";
+				reg = <0x65a00000 0x10000>;
+				interrupts = <0 134 4>;
+				tx-fifo-resize;
+			};
+		};
+
+		usb1: usb at 65d00000 {
+			compatible = "socionext,uniphier-pxs2-dwc3";
+			status = "disabled";
+			reg = <0x65d00000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
+			dwc3 at 65c00000 {
+				compatible = "snps,dwc3";
+				reg = <0x65c00000 0x10000>;
+				interrupts = <0 137 4>;
+				tx-fifo-resize;
+			};
+		};
+
+		nand: nand at 68000000 {
+			compatible = "socionext,denali-nand-v5b";
+			status = "disabled";
+			reg-names = "nand_data", "denali_reg";
+			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+			interrupts = <0 65 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_nand>;
+			clocks = <&sys_clk 2>;
+			nand-ecc-strength = <8>;
+		};
+	};
 };
+
+/include/ "uniphier-pinctrl.dtsi"
diff --git a/arch/arm/dts/uniphier-sld3.dtsi b/arch/arm/dts/uniphier-sld3.dtsi
index f5c5487..919cbff 100644
--- a/arch/arm/dts/uniphier-sld3.dtsi
+++ b/arch/arm/dts/uniphier-sld3.dtsi
@@ -50,12 +50,6 @@
 			compatible = "fixed-clock";
 			clock-frequency = <50000000>;
 		};
-
-		iobus_clk: iobus_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <100000000>;
-		};
 	};
 
 	soc {
@@ -251,7 +245,7 @@
 			interrupts = <0 41 1>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_i2c0>;
-			clocks = <&iobus_clk>;
+			clocks = <&sys_clk 1>;
 			clock-frequency = <100000>;
 		};
 
@@ -262,7 +256,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			interrupts = <0 42 1>;
-			clocks = <&iobus_clk>;
+			clocks = <&sys_clk 1>;
 			clock-frequency = <100000>;
 		};
 
@@ -273,7 +267,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			interrupts = <0 43 1>;
-			clocks = <&iobus_clk>;
+			clocks = <&sys_clk 1>;
 			clock-frequency = <100000>;
 		};
 
@@ -284,7 +278,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			interrupts = <0 44 1>;
-			clocks = <&iobus_clk>;
+			clocks = <&sys_clk 1>;
 			clock-frequency = <100000>;
 		};
 
@@ -295,7 +289,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			interrupts = <0 45 1>;
-			clocks = <&iobus_clk>;
+			clocks = <&sys_clk 1>;
 			clock-frequency = <400000>;
 		};
 
@@ -339,9 +333,12 @@
 			pinctrl-0 = <&pinctrl_emmc>;
 			pinctrl-1 = <&pinctrl_emmc_1v8>;
 			clocks = <&mio_clk 1>;
+			reset-names = "host", "bridge";
 			resets = <&mio_rst 1>, <&mio_rst 4>;
 			bus-width = <8>;
 			non-removable;
+			cap-mmc-highspeed;
+			cap-mmc-hw-reset;
 		};
 
 		sd: sdhc at 5a500000 {
@@ -353,8 +350,13 @@
 			pinctrl-0 = <&pinctrl_sd>;
 			pinctrl-1 = <&pinctrl_sd_1v8>;
 			clocks = <&mio_clk 0>;
+			reset-names = "host", "bridge";
 			resets = <&mio_rst 0>, <&mio_rst 3>;
 			bus-width = <4>;
+			cap-sd-highspeed;
+			sd-uhs-sdr12;
+			sd-uhs-sdr25;
+			sd-uhs-sdr50;
 		};
 
 		usb0: usb at 5a800100 {
@@ -406,7 +408,8 @@
 		};
 
 		soc-glue at 5f800000 {
-			compatible = "simple-mfd", "syscon";
+			compatible = "socionext,uniphier-sld3-soc-glue",
+				     "simple-mfd", "syscon";
 			reg = <0x5f800000 0x2000>;
 			u-boot,dm-pre-reloc;
 
@@ -422,7 +425,7 @@
 		};
 
 		sysctrl at f1840000 {
-			compatible = "socionext,uniphier-sysctrl",
+			compatible = "socionext,uniphier-sld3-sysctrl",
 				     "simple-mfd", "syscon";
 			reg = <0xf1840000 0x4000>;
 
@@ -438,9 +441,13 @@
 		};
 
 		nand: nand at f8000000 {
-			compatible = "denali,denali-nand-dt";
-			reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
+			compatible = "socionext,denali-nand-v5a";
+			status = "disabled";
 			reg-names = "nand_data", "denali_reg";
+			reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
+			interrupts = <0 65 4>;
+			clocks = <&sys_clk 2>;
+			nand-ecc-strength = <8>;
 		};
 	};
 };
diff --git a/arch/arm/dts/uniphier-sld8.dtsi b/arch/arm/dts/uniphier-sld8.dtsi
index b8f6d67..31252a4 100644
--- a/arch/arm/dts/uniphier-sld8.dtsi
+++ b/arch/arm/dts/uniphier-sld8.dtsi
@@ -7,7 +7,7 @@
  * SPDX-License-Identifier:	GPL-2.0+	X11
  */
 
-/include/ "uniphier-common32.dtsi"
+/include/ "skeleton.dtsi"
 
 / {
 	compatible = "socionext,uniphier-sld8";
@@ -25,313 +25,437 @@
 		};
 	};
 
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
 	clocks {
-		arm_timer_clk: arm_timer_clk {
-			#clock-cells = <0>;
+		refclk: ref {
 			compatible = "fixed-clock";
-			clock-frequency = <50000000>;
+			#clock-cells = <0>;
+			clock-frequency = <25000000>;
 		};
 
-		iobus_clk: iobus_clk {
+		arm_timer_clk: arm_timer_clk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
-			clock-frequency = <100000000>;
+			clock-frequency = <50000000>;
 		};
 	};
-};
 
-&soc {
-	l2: l2-cache at 500c0000 {
-		compatible = "socionext,uniphier-system-cache";
-		reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
-		interrupts = <0 174 4>, <0 175 4>;
-		cache-unified;
-		cache-size = <(256 * 1024)>;
-		cache-sets = <256>;
-		cache-line-size = <128>;
-		cache-level = <2>;
-	};
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		interrupt-parent = <&intc>;
+		u-boot,dm-pre-reloc;
+
+		l2: l2-cache at 500c0000 {
+			compatible = "socionext,uniphier-system-cache";
+			reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
+			      <0x506c0000 0x400>;
+			interrupts = <0 174 4>, <0 175 4>;
+			cache-unified;
+			cache-size = <(256 * 1024)>;
+			cache-sets = <256>;
+			cache-line-size = <128>;
+			cache-level = <2>;
+		};
 
-	port0x: gpio at 55000008 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000008 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		serial0: serial at 54006800 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006800 0x40>;
+			interrupts = <0 33 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart0>;
+			clocks = <&peri_clk 0>;
+			clock-frequency = <80000000>;
+		};
 
-	port1x: gpio at 55000010 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000010 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		serial1: serial at 54006900 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006900 0x40>;
+			interrupts = <0 35 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart1>;
+			clocks = <&peri_clk 1>;
+			clock-frequency = <80000000>;
+		};
 
-	port2x: gpio at 55000018 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000018 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		serial2: serial at 54006a00 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006a00 0x40>;
+			interrupts = <0 37 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart2>;
+			clocks = <&peri_clk 2>;
+			clock-frequency = <80000000>;
+		};
 
-	port3x: gpio at 55000020 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000020 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		serial3: serial at 54006b00 {
+			compatible = "socionext,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006b00 0x40>;
+			interrupts = <0 29 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart3>;
+			clocks = <&peri_clk 3>;
+			clock-frequency = <80000000>;
+		};
 
-	port4: gpio at 55000028 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000028 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port0x: gpio at 55000008 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000008 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port5x: gpio at 55000030 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000030 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port1x: gpio at 55000010 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000010 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port6x: gpio at 55000038 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000038 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port2x: gpio at 55000018 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000018 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port7x: gpio at 55000040 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000040 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port3x: gpio at 55000020 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000020 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port8x: gpio at 55000048 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000048 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port4: gpio at 55000028 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000028 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port9x: gpio at 55000050 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000050 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port5x: gpio at 55000030 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000030 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port10x: gpio at 55000058 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000058 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port6x: gpio at 55000038 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000038 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port11x: gpio at 55000060 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000060 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port7x: gpio at 55000040 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000040 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port12x: gpio at 55000068 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000068 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port8x: gpio at 55000048 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000048 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port13x: gpio at 55000070 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000070 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port9x: gpio at 55000050 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000050 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port14x: gpio at 55000078 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000078 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port10x: gpio at 55000058 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000058 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	port16x: gpio at 55000088 {
-		compatible = "socionext,uniphier-gpio";
-		reg = <0x55000088 0x8>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
+		port11x: gpio at 55000060 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000060 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	i2c0: i2c at 58400000 {
-		compatible = "socionext,uniphier-i2c";
-		status = "disabled";
-		reg = <0x58400000 0x40>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 41 1>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c0>;
-		clocks = <&iobus_clk>;
-		clock-frequency = <100000>;
-	};
+		port12x: gpio at 55000068 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000068 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	i2c1: i2c at 58480000 {
-		compatible = "socionext,uniphier-i2c";
-		status = "disabled";
-		reg = <0x58480000 0x40>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 42 1>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c1>;
-		clocks = <&iobus_clk>;
-		clock-frequency = <100000>;
-	};
+		port13x: gpio at 55000070 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000070 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	/* chip-internal connection for DMD */
-	i2c2: i2c at 58500000 {
-		compatible = "socionext,uniphier-i2c";
-		reg = <0x58500000 0x40>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 43 1>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c2>;
-		clocks = <&iobus_clk>;
-		clock-frequency = <400000>;
-	};
+		port14x: gpio at 55000078 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000078 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	i2c3: i2c at 58580000 {
-		compatible = "socionext,uniphier-i2c";
-		status = "disabled";
-		reg = <0x58580000 0x40>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupts = <0 44 1>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_i2c3>;
-		clocks = <&iobus_clk>;
-		clock-frequency = <100000>;
-	};
+		port16x: gpio at 55000088 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000088 0x8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 
-	sd: sdhc at 5a400000 {
-		compatible = "socionext,uniphier-sdhc";
-		status = "disabled";
-		reg = <0x5a400000 0x200>;
-		interrupts = <0 76 4>;
-		pinctrl-names = "default", "1.8v";
-		pinctrl-0 = <&pinctrl_sd>;
-		pinctrl-1 = <&pinctrl_sd_1v8>;
-		clocks = <&mio_clk 0>;
-		reset-names = "host", "bridge";
-		resets = <&mio_rst 0>, <&mio_rst 3>;
-		bus-width = <4>;
-	};
+		i2c0: i2c at 58400000 {
+			compatible = "socionext,uniphier-i2c";
+			status = "disabled";
+			reg = <0x58400000 0x40>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 41 1>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c0>;
+			clocks = <&peri_clk 4>;
+			clock-frequency = <100000>;
+		};
 
-	emmc: sdhc at 5a500000 {
-		compatible = "socionext,uniphier-sdhc";
-		status = "disabled";
-		interrupts = <0 78 4>;
-		reg = <0x5a500000 0x200>;
-		pinctrl-names = "default", "1.8v";
-		pinctrl-0 = <&pinctrl_emmc>;
-		pinctrl-1 = <&pinctrl_emmc_1v8>;
-		clocks = <&mio_clk 1>;
-		reset-names = "host", "bridge", "hw-reset";
-		resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
-		bus-width = <8>;
-		non-removable;
-	};
+		i2c1: i2c at 58480000 {
+			compatible = "socionext,uniphier-i2c";
+			status = "disabled";
+			reg = <0x58480000 0x40>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 42 1>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c1>;
+			clocks = <&peri_clk 5>;
+			clock-frequency = <100000>;
+		};
 
-	usb0: usb at 5a800100 {
-		compatible = "socionext,uniphier-ehci", "generic-ehci";
-		status = "disabled";
-		reg = <0x5a800100 0x100>;
-		interrupts = <0 80 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_usb0>;
-		clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
-		resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
-			 <&mio_rst 12>;
-	};
+		/* chip-internal connection for DMD */
+		i2c2: i2c at 58500000 {
+			compatible = "socionext,uniphier-i2c";
+			reg = <0x58500000 0x40>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 43 1>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c2>;
+			clocks = <&peri_clk 6>;
+			clock-frequency = <400000>;
+		};
 
-	usb1: usb at 5a810100 {
-		compatible = "socionext,uniphier-ehci", "generic-ehci";
-		status = "disabled";
-		reg = <0x5a810100 0x100>;
-		interrupts = <0 81 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_usb1>;
-		clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
-		resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
-			 <&mio_rst 13>;
-	};
+		i2c3: i2c at 58580000 {
+			compatible = "socionext,uniphier-i2c";
+			status = "disabled";
+			reg = <0x58580000 0x40>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 44 1>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c3>;
+			clocks = <&peri_clk 7>;
+			clock-frequency = <100000>;
+		};
 
-	usb2: usb at 5a820100 {
-		compatible = "socionext,uniphier-ehci", "generic-ehci";
-		status = "disabled";
-		reg = <0x5a820100 0x100>;
-		interrupts = <0 82 4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_usb2>;
-		clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
-		resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
-			 <&mio_rst 14>;
-	};
+		system_bus: system-bus at 58c00000 {
+			compatible = "socionext,uniphier-system-bus";
+			status = "disabled";
+			reg = <0x58c00000 0x400>;
+			#address-cells = <2>;
+			#size-cells = <1>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_system_bus>;
+		};
 
-	aidet at 61830000 {
-		compatible = "simple-mfd", "syscon";
-		reg = <0x61830000 0x200>;
-	};
-};
+		smpctrl at 59800000 {
+			compatible = "socionext,uniphier-smpctrl";
+			reg = <0x59801000 0x400>;
+		};
 
-&refclk {
-	clock-frequency = <25000000>;
-};
+		mioctrl at 59810000 {
+			compatible = "socionext,uniphier-sld8-mioctrl",
+				     "simple-mfd", "syscon";
+			reg = <0x59810000 0x800>;
 
-&serial0 {
-	clock-frequency = <80000000>;
-};
+			mio_clk: clock {
+				compatible = "socionext,uniphier-sld8-mio-clock";
+				#clock-cells = <1>;
+			};
 
-&serial1 {
-	clock-frequency = <80000000>;
-};
+			mio_rst: reset {
+				compatible = "socionext,uniphier-sld8-mio-reset";
+				#reset-cells = <1>;
+			};
+		};
 
-&serial2 {
-	clock-frequency = <80000000>;
-};
+		perictrl at 59820000 {
+			compatible = "socionext,uniphier-sld8-perictrl",
+				     "simple-mfd", "syscon";
+			reg = <0x59820000 0x200>;
 
-&serial3 {
-	interrupts = <0 29 4>;
-	clock-frequency = <80000000>;
-};
+			peri_clk: clock {
+				compatible = "socionext,uniphier-sld8-peri-clock";
+				#clock-cells = <1>;
+			};
 
-&mio_clk {
-	compatible = "socionext,uniphier-sld8-mio-clock";
-};
+			peri_rst: reset {
+				compatible = "socionext,uniphier-sld8-peri-reset";
+				#reset-cells = <1>;
+			};
+		};
 
-&mio_rst {
-	compatible = "socionext,uniphier-sld8-mio-reset";
-};
+		sd: sdhc at 5a400000 {
+			compatible = "socionext,uniphier-sdhc";
+			status = "disabled";
+			reg = <0x5a400000 0x200>;
+			interrupts = <0 76 4>;
+			pinctrl-names = "default", "1.8v";
+			pinctrl-0 = <&pinctrl_sd>;
+			pinctrl-1 = <&pinctrl_sd_1v8>;
+			clocks = <&mio_clk 0>;
+			reset-names = "host", "bridge";
+			resets = <&mio_rst 0>, <&mio_rst 3>;
+			bus-width = <4>;
+			cap-sd-highspeed;
+			sd-uhs-sdr12;
+			sd-uhs-sdr25;
+			sd-uhs-sdr50;
+		};
 
-&peri_clk {
-	compatible = "socionext,uniphier-sld8-peri-clock";
-};
+		emmc: sdhc at 5a500000 {
+			compatible = "socionext,uniphier-sdhc";
+			status = "disabled";
+			reg = <0x5a500000 0x200>;
+			interrupts = <0 78 4>;
+			pinctrl-names = "default", "1.8v";
+			pinctrl-0 = <&pinctrl_emmc>;
+			pinctrl-1 = <&pinctrl_emmc_1v8>;
+			clocks = <&mio_clk 1>;
+			reset-names = "host", "bridge";
+			resets = <&mio_rst 1>, <&mio_rst 4>;
+			bus-width = <8>;
+			non-removable;
+			cap-mmc-highspeed;
+			cap-mmc-hw-reset;
+		};
 
-&peri_rst {
-	compatible = "socionext,uniphier-sld8-peri-reset";
-};
+		usb0: usb at 5a800100 {
+			compatible = "socionext,uniphier-ehci", "generic-ehci";
+			status = "disabled";
+			reg = <0x5a800100 0x100>;
+			interrupts = <0 80 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb0>;
+			clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
+			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
+				 <&mio_rst 12>;
+		};
 
-&pinctrl {
-	compatible = "socionext,uniphier-sld8-pinctrl";
-};
+		usb1: usb at 5a810100 {
+			compatible = "socionext,uniphier-ehci", "generic-ehci";
+			status = "disabled";
+			reg = <0x5a810100 0x100>;
+			interrupts = <0 81 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb1>;
+			clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
+			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
+				 <&mio_rst 13>;
+		};
 
-&sys_clk {
-	compatible = "socionext,uniphier-sld8-clock";
-};
+		usb2: usb at 5a820100 {
+			compatible = "socionext,uniphier-ehci", "generic-ehci";
+			status = "disabled";
+			reg = <0x5a820100 0x100>;
+			interrupts = <0 82 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb2>;
+			clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
+			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
+				 <&mio_rst 14>;
+		};
+
+		soc-glue at 5f800000 {
+			compatible = "socionext,uniphier-sld8-soc-glue",
+				     "simple-mfd", "syscon";
+			reg = <0x5f800000 0x2000>;
+			u-boot,dm-pre-reloc;
+
+			pinctrl: pinctrl {
+				compatible = "socionext,uniphier-sld8-pinctrl";
+			};
+		};
+
+		timer at 60000200 {
+			compatible = "arm,cortex-a9-global-timer";
+			reg = <0x60000200 0x20>;
+			interrupts = <1 11 0x104>;
+			clocks = <&arm_timer_clk>;
+		};
 
-&sys_rst {
-	compatible = "socionext,uniphier-sld8-reset";
+		timer at 60000600 {
+			compatible = "arm,cortex-a9-twd-timer";
+			reg = <0x60000600 0x20>;
+			interrupts = <1 13 0x104>;
+			clocks = <&arm_timer_clk>;
+		};
+
+		intc: interrupt-controller at 60001000 {
+			compatible = "arm,cortex-a9-gic";
+			reg = <0x60001000 0x1000>,
+			      <0x60000100 0x100>;
+			#interrupt-cells = <3>;
+			interrupt-controller;
+		};
+
+		aidet at 61830000 {
+			compatible = "simple-mfd", "syscon";
+			reg = <0x61830000 0x200>;
+		};
+
+		sysctrl at 61840000 {
+			compatible = "socionext,uniphier-sld8-sysctrl",
+				     "simple-mfd", "syscon";
+			reg = <0x61840000 0x10000>;
+
+			sys_clk: clock {
+				compatible = "socionext,uniphier-sld8-clock";
+				#clock-cells = <1>;
+			};
+
+			sys_rst: reset {
+				compatible = "socionext,uniphier-sld8-reset";
+				#reset-cells = <1>;
+			};
+		};
+
+		nand: nand at 68000000 {
+			compatible = "socionext,denali-nand-v5a";
+			status = "disabled";
+			reg-names = "nand_data", "denali_reg";
+			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+			interrupts = <0 65 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_nand>;
+			clocks = <&sys_clk 2>;
+			nand-ecc-strength = <8>;
+		};
+	};
 };
+
+/include/ "uniphier-pinctrl.dtsi"
-- 
2.7.4