[U-Boot] Warm reset problems in U-Boot
Oehen, Marcel
marcel.oehen at siemens.com
Thu Dec 8 09:59:32 CET 2016
Dear sir or madam,
We are using an Altera cyclone V SoC FPGA and have a problem on warm reset in the U-Boot environment. I would be very grateful if you could send this e-mail to a responsible person.
It is possible to answer in English or German.
Kind regards,
Marcel Oehen
Siemens Schweiz AG
Mobility
Hammerweg 1
8304 Wallisellen, Switzerland
Tel.: +41 585 580930
mailto:marcel.oehen at siemens.com, www.siemens.ch<http://www.siemens.ch>
www.siemens.com/ingenuityforlife<https://siemens.com/ingenuityforlife>
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PROBLEM:
After a warm reset, we can not reconfigurate the FPGA over a "Altera Remote Update IP Core" in the uboot environment. If we read or write data from/to the base address 0xc0060000 (0xc0000000 HPS2FPGA AXI Bridge + 0x60000 Remote Update IP Core) we get the message in the uboot console and it is doing a reset:
********************************************************************************
* Error Message
********************************************************************************
data abort
MAYBE you should read doc/README.arm-unaligned-accesses
pc : [<0ff9a570>] lr : [<0ff9a565>]
sp : 0ff325f8 ip : 00000002 fp : 0ff33868
r10: 0ff33888 r9 : 00000001 r8 : 0ff32f60
r7 : 0ff32616 r6 : 00000000 r5 : 0ff32617 r4 : 00780000
r3 : c0000000 r2 : 00000076 r1 : 0000000a r0 : 00000014
Flags: nzcv IRQs on FIQs off Mode SVC_32
Resetting CPU ...
resetting ...
U-Boot SPL 2013.01.01-svn2322 (Dec 06 2016 - 12:04:55)
BOARD : Altera SOCFPGA Cyclone V Board
CLOCK: EOSC1 clock 50000 KHz
......
......
********************************************************************************
GENERAL INFORMATION:
We have all our software images stored in a QSPI flash (Preloader, DeviceTree, Uboot, SW-Image 0, SW-Image1, SW-Image2) except the fpga image is in the EPCQ flash (Addr: 0x0 FPGA-Image0, Addr: 0x780000 FPGA-Image1). After a cold resest the preloader will be loaded after the uboot. The uboot write into the RU_PAGE_SELECT register (base address: 0xc006000C) from the "Altera Remote Update IP Core" the address of the FPGA-Image0 (0x780000) and triggers a reconfiguration with writing "1" into the RU_RECONFIG register. The fpga reconfiguration is working and the kernel is booting one of these 3 software images. When we are doing a reboot (shutdown -r) the device is doing a warm reset. (side note: we had a problem to reboot the device with a 4Bit QSPI flash. We adapted our hardware and resets the QSPI flash with the nRST signal -> We changed the default value to 0x20000 (rstmgr, register counts, name nrstcnt = 0x20000).
WHAT WE TRIED:
We tried to reconfigure (cf. "Reconfig FPGA!...") the fpga with a *.rbf stored on the sd card + we disable and enable all bridges. This works fine on a warm and cold reset (cf. "fpga Status register: mode 0x4" -> FPGA in User Mode).
After the console print ("START -------------") we are reading the register from a region global register and from the Altera Remote Update IP core the RU_PAGE_SELECT regsiter write 0x780000 into this register and triggers a reconfiguration. But this works only on a cold reset!
********************************************************************************
* Cold reset start up
********************************************************************************
U-Boot 2013.01.01 (Dec 07 2016 - 14:19:06)
CPU : Altera SOCFPGA Platform
BOARD : Altera SOCFPGA Cyclone V Board
I2C: ready
DRAM: 256 MiB
MMC: ALTERA DWMMC: 0
SF: Read data capture delay calibrated to 4 (1 - 7)
SF: Detected N25Q00 with page size 65536, total: 134217728
In: serial
Out: serial
Err: serial
Skipped ethaddr assignment due to invalid EMAC address in EEPROM
Net: mii0
Warning: failed to set MAC address
Hit any key to stop autoboot: 0
set cycles
tmp1: 0x200000a
fpga Status register: 0x9c
Reconfig FPGA!...
## Starting application at 0x0FF78550 ...
## Application terminated, rc = 0x0
reading output_file_128.rbf
4244820 bytes read in 236 ms (17.2 MiB/s)
## Starting application at 0x0FF78550 ...
## Application terminated, rc = 0x0
done!
fpga Status register: mode 0x4
fpga Status register: msel 0x13
Cold reset detected!
ENV_NAME_BOOT_MODE: 0
reconfiguration GW factory
START -------------
(1xx) RegionGlobal: 0x0
(2xx) RU_PAGE_SELECT: 0x0
(1) epcqGatewareImageAddress: 0x780000
(2*)
(2)
(3)
(4)
(5)
RU_RECONFIG_TRIGGER_CONDITIONS: 0x4
RU_PAGE_SELECT: 0x0
**********************************************
SND-Settings
qspibootimageaddr: 0x400000
snd_statusSoftwareFactory: 0
snd_statusSoftwareUpdated0: 1
snd_statusSoftwareUpdated1: 1
snd_versionSoftwareFactory: -
snd_versionSoftwareUpdated0: -
snd_versionSoftwareUpdated1: -
snd_watchdogOccurred: 0
**********************************************
## Starting application at 0x0FF78550 ...
## Application terminated, rc = 0x0
SF: Detected N25Q00 with page size 65536, total: 134217728
## Booting kernel from Legacy Image at 00007fc0 ...
Image Name: Linux kernel
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size: 16114704 Bytes = 15.4 MiB
Load Address: 00008000
Entry Point: 00008000
Verifying Checksum ... OK
## Flattened Device Tree blob at 00000100
Booting using the fdt blob at 0x00000100
XIP Kernel Image ... OK
OK
Loading Device Tree to 03ff6000, end 03fff058 ... OK
Starting kernel ...
[ 0.000000] Booting Linux on physical CPU 0x0
********************************************************************************
After a warm reset we have no access to the fpga over the Altera Remote Update IP core, although its the same uboot softwarecode!
********************************************************************************
* WARM reset start up
********************************************************************************
U-Boot SPL 2013.01.01-svn2322 (Dec 06 2016 - 12:04:55)
BOARD : Altera SOCFPGA Cyclone V Board
CLOCK: EOSC1 clock 50000 KHz
CLOCK: EOSC2 clock 50000 KHz
CLOCK: F2S_SDR_REF clock 0 KHz
CLOCK: F2S_PER_REF clock 0 KHz
CLOCK: MPU clock 800 MHz
CLOCK: DDR clock 400 MHz
CLOCK: UART clock 100000 KHz
CLOCK: MMC clock 50000 KHz
CLOCK: QSPI clock 400000 KHz
RESET: WARM
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION PASSED
SDRAM: 256 MiB
SF: Read data capture delay calibrated to 4 (1 - 7)
SF: Detected N25Q00 with page size 65536, total: 134217728
U-Boot 2013.01.01 (Dec 07 2016 - 14:19:06)
CPU : Altera SOCFPGA Platform
BOARD : Altera SOCFPGA Cyclone V Board
I2C: ready
DRAM: 256 MiB
MMC: ALTERA DWMMC: 0
SF: Read data capture delay calibrated to 4 (1 - 7)
SF: Detected N25Q00 with page size 65536, total: 134217728
In: serial
Out: serial
Err: serial
Skipped ethaddr assignment due to invalid EMAC address in EEPROM
Net: mii0
Warning: failed to set MAC address
Hit any key to stop autoboot: 0
set cycles
tmp1: 0x200000a
fpga Status register: 0x9c
Reconfig FPGA!...
## Starting application at 0x0FF78550 ...
## Application terminated, rc = 0x0
reading output_file_128.rbf
4244820 bytes read in 236 ms (17.2 MiB/s)
## Starting application at 0x0FF78550 ...
## Application terminated, rc = 0x0
done!
fpga Status register: mode 0x4
fpga Status register: msel 0x13
Warm reset detected!
ENV_NAME_BOOT_MODE: 0
do FPGA reset
reconfiguration GW factory
START -------------
data abort
MAYBE you should read doc/README.arm-unaligned-accesses
pc : [<0ff9a570>] lr : [<0ff9a565>]
sp : 0ff325f8 ip : 00000002 fp : 0ff33868
r10: 0ff33888 r9 : 00000001 r8 : 0ff32f60
r7 : 0ff32616 r6 : 00000000 r5 : 0ff32617 r4 : 00780000
r3 : c0000000 r2 : 00000076 r1 : 0000000a r0 : 00000014
Flags: nzcv IRQs on FIQs off Mode SVC_32
Resetting CPU ...
resetting ...
U-Boot SPL 2013.01.01-svn2322 (Dec 06 2016 - 12:04:55)
BOARD : Altera SOCFPGA Cyclone V Board
CLOCK: EOSC1 clock 50000 KHz
CLOCK: EOSC2 clock 50000 KHz
CLOCK: F2S_SDR_REF clock 0 KHz
CLOCK: F2S_PER_REF clock 0 KHz
CLOCK: MPU clock 800 MHz
CLOCK: DDR clock 400 MHz
CLOCK: UART clock 100000 KHz
CLOCK: MMC clock 50000 KHz
CLOCK: QSPI clock 400000 KHz
RESET: WARM
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION PASSED
SDRAM: 256 MiB
SF: Read data capture delay calibrated to 4 (1 - 7)
SF: Detected N25Q00 with page size 65536, total: 134217728
U-Boot 2013.01.01 (Dec 07 2016 - 14:19:06)
CPU : Altera SOCFPGA Platform
BOARD : Altera SOCFPGA Cyclone V Board
I2C: ready
DRAM: 256 MiB
MMC: ALTERA DWMMC: 0
SF: Read data capture delay calibrated to 4 (1 - 7)
SF: Detected N25Q00 with page size 65536, total: 134217728
In: serial
Out: serial
Err: serial
Skipped ethaddr assignment due to invalid EMAC address in EEPROM
Net: mii0
Warning: failed to set MAC address
Hit any key to stop autoboot: 0
SOCFPGA_CYCLONE5 #
********************************************************************************
This is the code snippet where the error occurs.
********************************************************************************
* Imported code snippet
********************************************************************************
#define ARU_BASE_ADDRESS 0xc0060000
#define FPGA_BASE_ADDRESS 0xc0000000
printf("START -------------\n");
tmp32 = (uint32_t) ioread32(FPGA_BASEADDRESS);
printf("(1xx) RegionGlobal: 0x%x\n", tmp32);
printf("(2xx) RU_PAGE_SELECT: 0x%x\n", ioread32(ALTREMOTE_BASE_ADDRESS + RU_PAGE_SELECT));
********************************************************************************
We have no idea why we have not access to the FPGA over the Altera Remote Update IP Core.
Please let me know if you need more details.
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