[U-Boot] [PATCH v2] arm: am33xx: Initialize EMIF REG_PR_OLD_COUNT for BBB and am335x-evm

Jyri Sarha jsarha at ti.com
Thu Dec 8 21:53:00 CET 2016


On 12/08/16 16:30, Tom Rini wrote:
> On Thu, Dec 08, 2016 at 12:19:01PM +0200, Jyri Sarha wrote:
> 
>> Initialize EMIF OCP_CONFIG registers REG_COS_COUNT_1, REG_COS_COUNT_2,
>> and REG_PR_OLD_COUNT field for Beaglebone-Black and am335x-evm. With
>> the default values LCDC suffers from DMA FIFO underflows and frame
>> synchronization lost errors. The initialization values are the highest
>> that work flawlessly when heavy memory load is generated by CPU. 32bpp
>> colors were used in the test. On BBB the video mode used 110MHz pixel
>> clock. The mode supported by the panel of am335x-evm uses 30MHz pixel
>> clock.
>>
>> Signed-off-by: Jyri Sarha <jsarha at ti.com>
> 
> Reviewed-by: Tom Rini <trini at konsulko.com>
> 
> But, does TI have a whitepaper or tech pub or anything that describes
> how one would calculate that value on a custom design?  Tweaking that
> for optimal usage is something I know happens in some cases and could be
> used in a lot more.  If there's a doc that explains how to figure it
> out, it would be good to link to it in the comments in the patch as
> well.  Since I don't know that such a thing does exist I'll reviewed-by
> it now tho.  Thanks!
> 

No there is no such thing. Actually the documentation of the whole
feature is quite limited in the public documentation. I could add a
reference to "7.3.3.5.2 Command Starvation" in am335x TRM with a remark
that "advanced bandwidth/prioritization control" the section mentions is
broken in all currently available am3 revisions and only
REG_PR_OLD_COUNT has real effect.

In practice the only rule to find an optimal value is to find as high as
possible REG_PR_OLD_COUNT value that does not produce LCDC FIFO
underflows under worst case scenario. The worst case happens when the
highest pixel clock videomode with maximum bpp is used while memory
subsystem is stressed by endless stream of writes hitting the same
memory memory bank (can be the same address).

Best regards,
Jyri


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