[U-Boot] [PATCH 1/2] armv8: Enable CPUECTLR.SMPEN for coherency

[Z.Q. Hou]

Hi Masahiro Yamada,

Thanks a lot for your comments!

> -----Original Message-----
> From: Masahiro Yamada [mailto:yamada.masahiro at socionext.com]
> Sent: 2016年12月19日 0:49
> To: Z.Q. Hou <zhiqiang.hou at nxp.com>
> Cc: U-Boot Mailing List <u-boot at lists.denx.de>; Albert ARIBAUD
> <albert.u.boot at aribaud.net>; Simon Glass <sjg at chromium.org>; Mingkai Hu
> <mingkai.hu at nxp.com>; york sun <york.sun at nxp.com>; Ashish Kumar
> <ashish.kumar at nxp.com>; Mateusz Kulikowski
> <mateusz.kulikowski at gmail.com>; Tom Rini <trini at konsulko.com>
> Subject: Re: [U-Boot] [PATCH 1/2] armv8: Enable CPUECTLR.SMPEN for
> coherency
> 
> 2016-12-15 15:08 GMT+09:00 Zhiqiang Hou <Zhiqiang.Hou at nxp.com>:
> > From: Mingkai Hu <mingkai.hu at nxp.com>
> >
> > For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is
> > set. The SMPEN bit should be set before enabling the data cache.
> > If not enabled, the cache is not coherent with other cores and data
> > corruption could occur.
> >
> > For A57/A72, SMPEN bit enables the processor to receive instruction
> > cache and TLB maintenance operations broadcast from other processors
> > in the cluster. This bit should be set before enabling the caches and
> > MMU, or performing any cache and TLB maintenance operations.
> >
> > Signed-off-by: Mingkai Hu <mingkai.hu at nxp.com>
> > Signed-off-by: Gong Qianyu <Qianyu.Gong at nxp.com>
> > Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski at gmail.com>
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
> > ---
> >  arch/arm/cpu/armv8/Kconfig | 12 ++++++++++++
> > arch/arm/cpu/armv8/start.S | 11 +++++++++++
> >  2 files changed, 23 insertions(+)
> >
> > diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
> > index 965a8d1..ce749f2 100644
> > --- a/arch/arm/cpu/armv8/Kconfig
> > +++ b/arch/arm/cpu/armv8/Kconfig
> > @@ -3,6 +3,18 @@ if ARM64
> >  config ARMV8_MULTIENTRY
> >          bool "Enable multiple CPUs to enter into U-Boot"
> >
> > +config ARMV8_SET_SMPEN
> > +        bool "Enable data coherency with other cores in cluster"
> > +        help
> > +          Cortex A53/57/72 cores require CPUECTLR_EL1.SMPEN set
> even
> > +          for single core systems. Unfortunately write access to this
> > +          register may be controlled by EL3/EL2 firmware. To be more
> > +          precise, by default (if there is EL2/EL3 firmware running)
> > +          this register is RO for NS EL1.
> > +          This switch can be used to avoid writing to CPUECTLR_EL1,
> > +          it can be safely enabled when El2/EL3 initialized SMPEN bit
> > +          or when CPU implementation doesn't include that register.
> > +
> 
> 
> If you run ARM Trusted Firmware, this bit has already been set correctly. (or if
> you implement your own trusted firmware, this bit should be set there.) In
> those cases, there is no need to touch it in U-Boot.
> 
> 
> The motivation for this commit is
> to boot the system without any firmware before U-Boot?

Yes

Thanks,
Zhiqiang