[U-Boot] [PATCH v3 16/26] sunxi: H3: add DRAM controller single bit delay support

[Maxime Ripard]

On Mon, Dec 19, 2016 at 01:50:06AM +0000, Andre Przywara wrote:
> From: Jens Kuske <jenskuske at gmail.com>
> 
> So far the DRAM driver for the H3 SoC (and apparently boot0/libdram as
> well) only applied coarse delay line settings, with one delay value for
> all the data lines in each byte lane and one value for the control lines.
> 
> Instead of setting the delays for whole bytes only allow setting it for
> each individual bit. Also add support for address/command lane delays.
> 
> For the purpose of this patch the rules for the existing coarse settings
> were just applied to the new scheme, so the actual register writes don't
> change for the H3. Other SoCs will utilize this feature later properly.
> 
> With a stock GCC 5.3.0 this increases the dram_sun8i_h3.o code size from
> 2296 to 2344 Bytes.
> 
> [Andre: move delay parameters into macros to ease later sharing, use
> 	defines for numbers of delay registers, extend commit message]
> 
> Signed-off-by: Jens Kuske <jenskuske at gmail.com>
> Signed-off-by: Andre Przywara <andre.przywara at arm.com>

I said it earlier, but some comments on these new fields would really
be welcome to document the structure and what values they're supposed
to hold.

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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