[U-Boot] [PATCH 2/4] ARM: zynq: Remove spi-max-frequency

[Michal Simek]

On 16.12.2016 18:28, Moritz Fischer wrote:
> Hi Michal,
> 
> On Fri, Dec 16, 2016 at 5:38 AM, Michal Simek <michal.simek at xilinx.com> wrote:
>> spi-max-frequency for spi bus depends on devices which are
>> connected to it. Remove this parameter from dtsi file.
>>
>> Signed-off-by: Michal Simek <michal.simek at xilinx.com>
>> ---
>>
>>  arch/arm/dts/zynq-7000.dtsi | 2 --
>>  1 file changed, 2 deletions(-)
>>
>> diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
>> index 668f54ec219d..fa9ee276cb59 100644
>> --- a/arch/arm/dts/zynq-7000.dtsi
>> +++ b/arch/arm/dts/zynq-7000.dtsi
>> @@ -177,7 +177,6 @@
>>                         interrupts = <0 26 4>;
>>                         clocks = <&clkc 25>, <&clkc 34>;
>>                         clock-names = "ref_clk", "pclk";
>> -                       spi-max-frequency = <166666700>;
>>                         #address-cells = <1>;
>>                         #size-cells = <0>;
>>                 };
>> @@ -190,7 +189,6 @@
>>                         interrupts = <0 49 4>;
>>                         clocks = <&clkc 26>, <&clkc 35>;
>>                         clock-names = "ref_clk", "pclk";
>> -                       spi-max-frequency = <166666700>;
>>                         #address-cells = <1>;
>>                         #size-cells = <0>;
>>                 };
>> --
>> 1.9.1
>>
> 
> While I agree with the patch, doesn't the drivers/spi/zynq_spi.c in u-boot
> (wrongly) use this to determine it's peripheral clock speed?
> 
> <snip>
> plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
>                                                       250000000);
> </snip>
> 
> and later in zynq_spi_set_speed() to calculate divisors?

Based on DT binding
spi-max-frequency - (required) Maximum SPI clocking speed of device in Hz

In node itself it should be max speed what controller can operate. Every
node should set it up for self and driver should be able to handle it.

Back to your point. plat->frequency setup is weird. It looks like input
reference clock to IP itself instead of max IP freq. I expect the reason
was that we couldn't get this value and Jagan was using it as workaround
how to get any value.
It should be simply clk_get_rate() and clk driver should return value.
And this value should be used in speed calculation. (Linux
Time to move zynq clk driver to DM to get these stuff for free.

Thanks,
Michal