[U-Boot] [PATCH v3 4/6] mmc: tegra: allow disabling external clock loopback

[Jaehoon Chung]

On 12/22/2016 01:26 PM, Marcel Ziswiler wrote:
> From: Marcel Ziswiler <marcel.ziswiler at toradex.com>
> 
> Introduce CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK to disable the external clock
> loopback and use the internal one on SDMMC3 as per the SDMMC_VENDOR_MISC_CNTRL_0
> register's SDMMC_SPARE1 bits being set to 0xfffd according to the TRM.
> 
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler at toradex.com>
> Reviewed-by: Simon Glass <sjg at chromium.org>

Reviewed-by: Jaehoon Chung <jh80.chung at samsung.com>

Best Regards,
Jaehoon Chung

> 
> ---
> 
> Changes in v3: None
> Changes in v2:
> - Added Simon's reviewed-by.
> - Added TODO(email) as suggested by Simon so it is clear this is
>   temporary and will be moved to device tree controlled approach once
>   proper kernel integration made it mainline.
> 
>  arch/arm/include/asm/arch-tegra/tegra_mmc.h |  2 ++
>  drivers/mmc/Kconfig                         | 11 +++++++++++
>  drivers/mmc/tegra_mmc.c                     | 16 ++++++++++++++++
>  3 files changed, 29 insertions(+)
> 
> diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
> index 64c848a..c40599a 100644
> --- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h
> +++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
> @@ -108,6 +108,8 @@ struct tegra_mmc {
>  #define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT			8
>  #define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK			(0xff << 8)
>  
> +#define TEGRA_MMC_MISCON_ENABLE_EXT_LOOPBACK			(1 << 17)
> +
>  #define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL			(1 << 0)
>  #define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE			(1 << 1)
>  #define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE			(1 << 2)
> diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
> index 18f0e97..6372876 100644
> --- a/drivers/mmc/Kconfig
> +++ b/drivers/mmc/Kconfig
> @@ -116,4 +116,15 @@ config TEGRA_MMC
>  	help
>  	  This selects support for SDHCI on Tegra SoCs.
>  
> +config TEGRA124_MMC_DISABLE_EXT_LOOPBACK
> +	bool "Disable external clock loopback"
> +	depends on TEGRA_MMC && TEGRA124
> +	help
> +	  Disable the external clock loopback and use the internal one on SDMMC3
> +	  as per the SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 bits
> +	  being set to 0xfffd according to the TRM.
> +
> +	  TODO(marcel.ziswiler at toradex.com): Move to device tree controlled
> +	  approach once proper kernel integration made it mainline.
> +
>  endmenu
> diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c
> index 97b1154..839b15d 100644
> --- a/drivers/mmc/tegra_mmc.c
> +++ b/drivers/mmc/tegra_mmc.c
> @@ -511,6 +511,22 @@ static int tegra_mmc_init(struct mmc *mmc)
>  
>  	tegra_mmc_reset(priv, mmc);
>  
> +#if defined(CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK)
> +	/*
> +	 * Disable the external clock loopback and use the internal one on
> +	 * SDMMC3 as per the SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
> +	 * bits being set to 0xfffd according to the TRM.
> +	 *
> +	 * TODO(marcel.ziswiler at toradex.com): Move to device tree controlled
> +	 * approach once proper kernel integration made it mainline.
> +	 */
> +	if (priv->reg == (void *)0x700b0400) {
> +		mask = readl(&priv->reg->venmiscctl);
> +		mask &= ~TEGRA_MMC_MISCON_ENABLE_EXT_LOOPBACK;
> +		writel(mask, &priv->reg->venmiscctl);
> +	}
> +#endif
> +
>  	priv->version = readw(&priv->reg->hcver);
>  	debug("host version = %x\n", priv->version);
>  
>