[U-Boot] [PATCHv3 2/2] armv8/fsl-lsch3: consolidate the clock system initialization

Z.Q. Hou zhiqiang.hou at nxp.com
Wed Dec 28 08:04:25 CET 2016


Hi,

Please ignore this patch!

Thanks,
Zhiqiang


> -----Original Message-----
> From: Zhiqiang Hou [mailto:Zhiqiang.Hou at nxp.com]
> Sent: 2016年12月28日 14:48
> To: u-boot at lists.denx.de; albert.u.boot at aribaud.net; york sun
> <york.sun at nxp.com>; Mingkai Hu <mingkai.hu at nxp.com>; Prabhakar
> Kushwaha <prabhakar.kushwaha at nxp.com>; Calvin Johnson
> <calvin.johnson at nxp.com>
> Cc: Z.Q. Hou <zhiqiang.hou at nxp.com>
> Subject: [PATCHv3 2/2] armv8/fsl-lsch3: consolidate the clock system
> initialization
> 
> From: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
> 
> This patch binds the sys_info->freq_systembus to Platform PLL, and
> implements the IPs' clock function individually.
> 
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
> ---
> V3:
>  - No change
> 
>  .../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 28
> ++++++++++++++++------  .../include/asm/arch-fsl-layerscape/immap_lsch3.h
> |  1 +
>  include/configs/ls2080a_common.h                   |  2 +-
>  3 files changed, 23 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> index a9b12a4..f8fefc7 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> @@ -88,11 +88,10 @@ void get_sys_info(struct sys_info *sys_info)  #endif
> #endif
> 
> +	/* The freq_systembus is used to record frequency of platform PLL */
>  	sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
>  			FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) &
>  			FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK;
> -	/* Platform clock is half of platform PLL */
> -	sys_info->freq_systembus /= 2;
>  	sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
>  			FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
>  			FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
> @@ -142,13 +141,13 @@ int get_clocks(void)
>  	struct sys_info sys_info;
>  	get_sys_info(&sys_info);
>  	gd->cpu_clk = sys_info.freq_processor[0];
> -	gd->bus_clk = sys_info.freq_systembus;
> +	gd->bus_clk = sys_info.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV;
>  	gd->mem_clk = sys_info.freq_ddrbus;
>  #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
>  	gd->arch.mem2_clk = sys_info.freq_ddrbus2;  #endif  #if
> defined(CONFIG_FSL_ESDHC)
> -	gd->arch.sdhc_clk = gd->bus_clk / 2;
> +	gd->arch.sdhc_clk = gd->bus_clk / CONFIG_SYS_FSL_SDHC_CLK_DIV;
>  #endif /* defined(CONFIG_FSL_ESDHC) */
> 
>  	if (gd->cpu_clk != 0)
> @@ -159,7 +158,7 @@ int get_clocks(void)
> 
>  /********************************************
>   * get_bus_freq
> - * return system bus freq in Hz
> + * return platform clock in Hz
>   *********************************************/
>  ulong get_bus_freq(ulong dummy)
>  {
> @@ -190,13 +189,28 @@ ulong get_ddr_freq(ulong ctrl_num)
>  	return gd->mem_clk;
>  }
> 
> +int get_i2c_freq(ulong dummy)
> +{
> +	return get_bus_freq(0) / CONFIG_SYS_FSL_I2C_CLK_DIV; }
> +
> +int get_dspi_freq(ulong dummy)
> +{
> +	return get_bus_freq(0) / CONFIG_SYS_FSL_DSPI_CLK_DIV; }
> +
> +int get_serial_clock(void)
> +{
> +	return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV; }
> +
>  unsigned int mxc_get_clock(enum mxc_clock clk)  {
>  	switch (clk) {
>  	case MXC_I2C_CLK:
> -		return get_bus_freq(0) / 2;
> +		return get_i2c_freq(0);
>  	case MXC_DSPI_CLK:
> -		return get_bus_freq(0) / 2;
> +		return get_dspi_freq(0);
>  	default:
>  		printf("Unsupported clock\n");
>  	}
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> index e18dcbd..cd25b48 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> @@ -159,6 +159,7 @@
>  #ifndef __ASSEMBLY__
>  struct sys_info {
>  	unsigned long freq_processor[CONFIG_MAX_CPUS];
> +	/* frequency of platform PLL */
>  	unsigned long freq_systembus;
>  	unsigned long freq_ddrbus;
>  #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
> diff --git a/include/configs/ls2080a_common.h
> b/include/configs/ls2080a_common.h
> index 2cae966..cf1185c 100644
> --- a/include/configs/ls2080a_common.h
> +++ b/include/configs/ls2080a_common.h
> @@ -97,7 +97,7 @@
>  #define CONFIG_CONS_INDEX       1
>  #define CONFIG_SYS_NS16550_SERIAL
>  #define CONFIG_SYS_NS16550_REG_SIZE     1
> -#define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
> +#define CONFIG_SYS_NS16550_CLK          (get_serial_clock())
> 
>  #define CONFIG_BAUDRATE			115200
>  #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600,
> 115200 }
> --
> 2.1.0.27.g96db324



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