[U-Boot] [PATCH 2/2] net: phy: micrel: fix divisor value for KSZ9031 phy skew

[Dinh Nguyen]

On 01/27/2016 07:26 PM, Måns Rullgård wrote:
> <dinguyen at opensource.altera.com> writes:
> 
>> From: Dinh Nguyen <dinguyen at opensource.altera.com>
>>
>> The picoseconds to register value divisor(ps_to_regval) should be 60 and not
>> 200. Linux has KSZ9031_PS_TO_REG defined to be 60 as well. 60 is the correct
>> divisor because the 4-bit skew values are defined from 0x0000(-420ps) to
>> 0xffff(480ps), increments of 60.
>>
>> For example, a DTS skew value of 420, represents 0ps delay, which should be 0x7.
>> With the previous divisor of 200, it would result in 0x2, which represents a
>> -300ps delay.
>>
>> With this patch, ethernet on the SoCFPGA DE0 Atlas is now able to work with
>> 1Gb ethernet.
> 
> Is this expected to make any difference on the Altera socdk?  Both with
> and without the patch, it takes a very long time (sometimes minutes) to
> negotiate a link, but once it does it works fine.
> 

The Altera socdk uses a different PHY, KSZ9021, so no, this patch will
not affect that hardware.

I'll check out your link issues on the socdk when I get a chance.

Dinh