[U-Boot] [PATCH v3] Enable snooping on transactions from CAAM block
Aneesh Bansal
aneesh.bansal at nxp.com
Wed Feb 3 09:22:54 CET 2016
> -----Original Message-----
> From: Huan Wang
> Sent: Tuesday, February 02, 2016 12:31 PM
> To: york sun <york.sun at nxp.com>; Aneesh Bansal <aneesh.bansal at nxp.com>; u-
> boot at lists.denx.de; Huan Wang-B18965 <Alison.Wang at freescale.com>
> Cc: Ruchika Gupta <ruchika.gupta at nxp.com>; Prabhakar Kushwaha
> <prabhakar.kushwaha at nxp.com>; Nitesh Lal <nitesh.lal at nxp.com>
> Subject: RE: [PATCH v3] Enable snooping on transactions from CAAM block
>
> Hi, York,
>
> > -----Original Message-----
> > From: york sun [mailto:york.sun at nxp.com]
> > Sent: Tuesday, February 02, 2016 1:06 AM
> > To: Aneesh Bansal; u-boot at lists.denx.de; Huan Wang-B18965
> > Cc: Ruchika Gupta; Prabhakar Kushwaha; Nitesh Lal
> > Subject: Re: [PATCH v3] Enable snooping on transactions from CAAM
> > block
> >
> > +Alison to comment on my question at the end of this email
> >
> > Aneesh,
> >
> > A few comments to this patch.
> >
> > First, please prefix the subject with a meaningful tag. In this case,
> > it should be armv7: ls1020a.
> >
> > On 01/17/2016 10:16 PM, Aneesh Bansal wrote:
> > > To enable snooping on CAAM transactions following programming is
> > > done
> > >
> > > 1. Enable core snooping (CCI interface, Core is Slave5 on CCI) This
> > > setting is also required for making the system coherent
> > >
> > > 2. CAAM IP lies behind SMMU3 in the system. Configure SMMU3 to do
> > > the
> > following:
> > > a) Program SCR to bypass transactions with stream ID other than that
> > > of CAAM
> > > b) Program S2CR to change memroy attributes of transactions with
> > > CAAM's stream ID (0x10) to cacheable.
> >
> > Second, the commit message should not exceed 72 characters.
> > Third, the commit message should explain why and what this patch is
> > doing. I don't see any change related to enabling snooping on CCI in
> > this patch.
> >
> > >
> > > Signed-off-by: Ruchika Gupta <ruchika.gupta at nxp.com>
> > > Signed-off-by: Nitesh Narayan Lal <nitesh.lal at nxp.com>
> > > Signed-off-by: Aneesh Bansal <aneesh.bansal at nxp.com>
> > > ---
> > > Changes in v3:
> > > Modified the commit message.
> > >
> > > Changes in v2:
> > > Avoid mixing the use of u32 and uint32_t.
> > > Using uint32_t at all places.
> > >
> > > arch/arm/include/asm/arch-ls102xa/config.h | 1 +
> > > .../include/asm/arch-ls102xa/ls102xa_stream_id.h | 34
> > ++++++++++++++++++++
> > > board/freescale/common/ls102xa_stream_id.c | 36
> > +++++++++++++++++++++-
> > > board/freescale/ls1021aqds/ls1021aqds.c | 4 +++
> > > board/freescale/ls1021atwr/ls1021atwr.c | 4 +++
> > > 5 files changed, 78 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/arch/arm/include/asm/arch-ls102xa/config.h
> > > b/arch/arm/include/asm/arch-ls102xa/config.h
> > > index f066480..f14ea2f 100644
> > > --- a/arch/arm/include/asm/arch-ls102xa/config.h
> > > +++ b/arch/arm/include/asm/arch-ls102xa/config.h
> > > @@ -38,6 +38,7 @@
> > > #define CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
> (CONFIG_SYS_IMMR +
> > 0x02100000)
> > > #define CONFIG_SYS_LS102XA_USB1_ADDR \
> > > (CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
> > > +#define CONFIG_SYS_SMMU3_ADDR
> (CONFIG_SYS_IMMR +
> > 0x300000)
> > >
> > > #define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000
> > > #define CONFIG_SYS_LS102XA_USB1_OFFSET 0x07600000
> > > diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
> > > b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
> > > index fa571b3..68e4e02 100644
> > > --- a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
> > > +++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
> > > @@ -6,6 +6,39 @@
> > >
> > > #ifndef __FSL_LS102XA_STREAM_ID_H_
> > > #define __FSL_LS102XA_STREAM_ID_H_
> > > +#define CONFIG_SMMU_NSCR_OFFSET 0x400
> > > +#define CONFIG_SMMU_SMR_OFFSET 0x800
> > > +#define CONFIG_SMMU_S2CR_OFFSET 0xc00
> > > +
> > > +#define SMMU_NSCR_CLIENTPD_SHIFT 0
> > > +#define SMMU_NSCR_MTCFG_SHIFT 20
> > > +
> > > +#define SMR_SMR_VALID_SHIFT 31
> > > +#define SMR_ID_MASK 0x7fff
> > > +#define SMR_MASK_SHIFT 16
> > > +
> > > +#define S2CR_WACFG_SHIFT 22
> > > +#define S2CR_WACFG_MASK 0x3
> > > +#define S2CR_WACFG_WRITE_ALLOCATE 0x2
> > > +
> > > +#define S2CR_RACFG_SHIFT 20
> > > +#define S2CR_RACFG_MASK 0x3
> > > +#define S2CR_RACFG_READ_ALLOCATE 0x2
> > > +
> > > +#define S2CR_TYPE_SHIFT 16
> > > +#define S2CR_TYPE_MASK 0x3
> > > +#define S2CR_TYPE_BYPASS 0x01
> > > +
> > > +#define S2CR_MEM_ATTR_SHIFT 12
> > > +#define S2CR_MEM_ATTR_MASK 0xf
> > > +#define S2CR_MEM_ATTR_CACHEABLE 0xa
> > > +
> > > +#define S2CR_MTCFG 0x00000800
> > > +
> > > +#define S2CR_SHCFG_SHIFT 8
> > > +#define S2CR_SHCFG_MASK 0x3
> > > +#define S2CR_SHCFG_OUTER_CACHEABLE 0x1
> > > +#define S2CR_SHCFG_INNER_CACHEABLE 0x2
> > >
> > > #include <fsl_sec.h>
> > >
> > > @@ -71,4 +104,5 @@ struct smmu_stream_id {
> > >
> > > void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int
> > > size); void ls102xa_config_smmu_stream_id(struct smmu_stream_id
> > > *id, uint32_t num);
> > > +void ls1021x_config_smmu3(uint32_t liodn);
> > > #endif
> > > diff --git a/board/freescale/common/ls102xa_stream_id.c
> > > b/board/freescale/common/ls102xa_stream_id.c
> > > index f434269..9ae29b8 100644
> > > --- a/board/freescale/common/ls102xa_stream_id.c
> > > +++ b/board/freescale/common/ls102xa_stream_id.c
> > > @@ -20,7 +20,7 @@ void ls102xa_config_smmu_stream_id(struct
> > > smmu_stream_id *id, uint32_t num) void
> > > ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size) {
> > > int i;
> > > - u32 liodn;
> > > + uint32_t liodn;
> > >
> > > for (i = 0; i < size; i++) {
> > > if (tbl[i].num_ids == 2)
> > > @@ -31,3 +31,37 @@ void ls1021x_config_caam_stream_id(struct
> > liodn_id_table *tbl, int size)
> > > out_le32((uint32_t *)(tbl[i].reg_offset), liodn);
> > > }
> > > }
> > > +
> > > +void ls1021x_config_smmu3(uint32_t liodn) {
> > > + uint32_t *addr;
> > > + uint32_t smr, s2cr, nscr;
> > > +
> > > + addr = (uint32_t *)(CONFIG_SYS_SMMU3_ADDR +
> > CONFIG_SMMU_NSCR_OFFSET);
> > > + /* SMMU NSCR configuration */
> > > + nscr = in_le32(addr);
> > > +
> > > + nscr = nscr & ~(1 << SMMU_NSCR_CLIENTPD_SHIFT |
> > > + 1 << SMMU_NSCR_MTCFG_SHIFT);
> > > + out_le32(addr, nscr);
> > > +
> > > + /* SMMU SMR configuration */
> > > + addr = (uint32_t *)(CONFIG_SYS_SMMU3_ADDR +
> > CONFIG_SMMU_SMR_OFFSET);
> > > +
> > > + smr = 0;
> > > + smr = smr & (~(SMR_ID_MASK << SMR_MASK_SHIFT));
> > > + smr = smr | (1 << SMR_SMR_VALID_SHIFT) | liodn;
> > > +
> > > + out_le32(addr, smr);
> > > +
> > > + /* SMMU S2CR configuration */
> > > + addr = (uint32_t *)(CONFIG_SYS_SMMU3_ADDR +
> > CONFIG_SMMU_S2CR_OFFSET);
> > > + s2cr = (S2CR_WACFG_WRITE_ALLOCATE << S2CR_WACFG_SHIFT) |
> > > + (S2CR_RACFG_READ_ALLOCATE << S2CR_RACFG_SHIFT) |
> > > + (S2CR_TYPE_BYPASS << S2CR_TYPE_SHIFT) |
> > > + (S2CR_MEM_ATTR_CACHEABLE << S2CR_MEM_ATTR_SHIFT) |
> > > + S2CR_MTCFG |
> > > + (S2CR_SHCFG_OUTER_CACHEABLE << S2CR_SHCFG_SHIFT);
> > > +
> > > + out_le32(addr, s2cr);
> > > +}
> > > diff --git a/board/freescale/ls1021aqds/ls1021aqds.c
> > > b/board/freescale/ls1021aqds/ls1021aqds.c
> > > index be3358a..ca1ea61 100644
> > > --- a/board/freescale/ls1021aqds/ls1021aqds.c
> > > +++ b/board/freescale/ls1021aqds/ls1021aqds.c
> > > @@ -481,6 +481,10 @@ int board_init(void)
> > > ARRAY_SIZE(sec_liodn_tbl));
> > > ls102xa_config_smmu_stream_id(dev_stream_id,
> > > ARRAY_SIZE(dev_stream_id));
> > > + /* Configure SMMU3 to make transactions with CAAM stream ID
> > > + * as cacheable
> > > + */
> > > + ls1021x_config_smmu3(0x10);
> > >
> > > #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
> > > enable_layerscape_ns_access();
> > > diff --git a/board/freescale/ls1021atwr/ls1021atwr.c
> > > b/board/freescale/ls1021atwr/ls1021atwr.c
> > > index 8eaff5f..ae62bca 100644
> > > --- a/board/freescale/ls1021atwr/ls1021atwr.c
> > > +++ b/board/freescale/ls1021atwr/ls1021atwr.c
> > > @@ -528,6 +528,10 @@ int board_init(void)
> > > ARRAY_SIZE(sec_liodn_tbl));
> > > ls102xa_config_smmu_stream_id(dev_stream_id,
> > > ARRAY_SIZE(dev_stream_id));
> > > + /* Configure SMMU3 to make transactions with CAAM stream ID
> > > + * as cacheable
> > > + */
> > > + ls1021x_config_smmu3(0x10);
> > >
> > > #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
> > > enable_layerscape_ns_access();
> > >
> >
> > Alison,
> >
> > Is the SMMU specific to these two boards? Shall it be moved to soc file?
> > The same question goes with stream_id as well.
> [Alison Wang] SMMU is not specific to these two boards. It should be moved to soc
> file with stream_id.
>
>
> Best Regards,
> Alison Wang
I discussed this with Alison.
Alison would be sending a patch to move the existing SMMU code to soc specific file.
I would be rebasing my changes on top of that patch.
Regards,
Aneesh Bansal
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