[U-Boot] [PATCH] armv8: ls2080: Update SerDes2 table for 0x45 & 0x47 protocol

[Pratiyush Mohan Srivastava]

LANE A of SerDes 2 Protocol 0x45 & 0x47 are SGMII9 and PCIE3
respectively.
So Update SerDes2 table for 0x45 & 0x47 protocol.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava at nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c
index ea3114c..cc4b79b 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c
@@ -56,9 +56,9 @@ static struct serdes_config serdes2_cfg_tbl[] = {
 	{0x42, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } },
 	{0x43, {PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } },
 	{0x44, {PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } },
-	{0x45, {PCIE3, SGMII10, SGMII11, SGMII12, PCIE4, SGMII14, SGMII15,
+	{0x45, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, SGMII14, SGMII15,
 		SGMII16 } },
-	{0x47, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, PCIE4,
+	{0x47, {PCIE3, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, PCIE4,
 		PCIE4 } },
 	{0x49, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1,
 		SATA2 } },
-- 
1.9.1