[U-Boot] [PATCH v4 8/8] dm: x86: spi: Convert ICH SPI driver to driver model PCI API
Bin Meng
bmeng.cn at gmail.com
Mon Jan 18 08:44:44 CET 2016
Hi Simon,
On Sun, Jan 17, 2016 at 7:44 AM, Simon Glass <sjg at chromium.org> wrote:
> At present this SPI driver works by searching the PCI buses for its
> peripheral. It also uses the legacy PCI API.
>
> In addition the driver has code to determine the type of Intel PCH that is
> used (version 7 or version 9). Now that we have proper PCH drivers we can
> use those to obtain the information we need.
>
> While the device tree has a node for the SPI peripheral it is not in the
> right place. It should be on the PCI bus as a sub-peripheral of the LPC
> device.
>
> Update the device tree files to show the SPI controller within the PCH, so
> that PCI access works as expected.
>
> Signed-off-by: Simon Glass <sjg at chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn at gmail.com>
> ---
>
> Changes in v4:
> - Add BIOS_CTRL address for PCH9
>
> Changes in v3:
> - Use the set_spi_protect() PCH method
>
> Changes in v2:
> - Adjust code for earlier commits
> - Move the SPI base code into the PCH drivers
>
> arch/x86/cpu/coreboot/pci.c | 3 +-
> arch/x86/cpu/irq.c | 7 +-
> arch/x86/cpu/ivybridge/bd82x6x.c | 47 ++++++++++-
> arch/x86/dts/bayleybay.dts | 160 +++++++++++++++++++-----------------
> arch/x86/dts/broadwell_som-6896.dts | 23 ++++--
> arch/x86/dts/chromebook_link.dts | 5 +-
> arch/x86/dts/chromebox_panther.dts | 33 ++++----
> arch/x86/dts/crownbay.dts | 150 +++++++++++++++++----------------
> arch/x86/dts/galileo.dts | 98 +++++++++++-----------
> arch/x86/dts/minnowmax.dts | 158 ++++++++++++++++++-----------------
> arch/x86/dts/qemu-x86_i440fx.dts | 26 +++---
> arch/x86/dts/qemu-x86_q35.dts | 38 +++++----
> drivers/spi/ich.c | 152 ++++++++--------------------------
> 13 files changed, 458 insertions(+), 442 deletions(-)
>
[snip]
> diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
> index 84231b3..ff739d4 100644
> --- a/arch/x86/dts/crownbay.dts
> +++ b/arch/x86/dts/crownbay.dts
> @@ -72,17 +72,6 @@
> stdout-path = "/serial";
> };
>
> - spi {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "intel,ich-spi";
> - spi-flash at 0 {
> - reg = <0>;
> - compatible = "sst,25vf016b", "spi-flash";
> - memory-map = <0xffe00000 0x00200000>;
> - };
> - };
> -
> microcode {
> update at 0 {
> #include "microcode/m0220661105_cv.dtsi"
> @@ -105,6 +94,18 @@
> u-boot,dm-pre-reloc;
> reg = <0x0000b800 0x0 0x0 0x0 0x0>;
>
> + spi {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "intel,ich-spi";
> + spi-flash at 0 {
> + reg = <0>;
> + compatible = "sst,25vf016b",
> + "spi-flash";
> + memory-map = <0xffe00000 0x00200000>;
> + };
> + };
> +
Oops! This breaks Crown Bay from booting anymore. This should be moved
after irq-router, to be a sub-node of pch.
> topcliff at 0,0 {
> #address-cells = <3>;
> #size-cells = <2>;
> @@ -170,68 +171,73 @@
> };
> };
>
> - irq-router at 1f,0 {
> + pch at 1f,0 {
> reg = <0x0000f800 0 0 0 0>;
> - compatible = "intel,irq-router";
> - intel,pirq-config = "pci";
> - intel,pirq-link = <0x60 8>;
> - intel,pirq-mask = <0xcee0>;
> - intel,pirq-routing = <
> - /* TunnelCreek PCI devices */
> - PCI_BDF(0, 2, 0) INTA PIRQE
> - PCI_BDF(0, 3, 0) INTA PIRQF
> - PCI_BDF(0, 23, 0) INTA PIRQA
> - PCI_BDF(0, 23, 0) INTB PIRQB
> - PCI_BDF(0, 23, 0) INTC PIRQC
> - PCI_BDF(0, 23, 0) INTD PIRQD
> - PCI_BDF(0, 24, 0) INTA PIRQB
> - PCI_BDF(0, 24, 0) INTB PIRQC
> - PCI_BDF(0, 24, 0) INTC PIRQD
> - PCI_BDF(0, 24, 0) INTD PIRQA
> - PCI_BDF(0, 25, 0) INTA PIRQC
> - PCI_BDF(0, 25, 0) INTB PIRQD
> - PCI_BDF(0, 25, 0) INTC PIRQA
> - PCI_BDF(0, 25, 0) INTD PIRQB
> - PCI_BDF(0, 26, 0) INTA PIRQD
> - PCI_BDF(0, 26, 0) INTB PIRQA
> - PCI_BDF(0, 26, 0) INTC PIRQB
> - PCI_BDF(0, 26, 0) INTD PIRQC
> - PCI_BDF(0, 27, 0) INTA PIRQG
> - /*
> - * Topcliff PCI devices
> - *
> - * Note on the Crown Bay board, Topcliff chipset
> - * is connected to TunnelCreek PCIe port 0, so
> - * its bus number is 1 for its PCIe port and 2
> - * for its PCI devices per U-Boot current PCI
> - * bus enumeration algorithm.
> - */
> - PCI_BDF(1, 0, 0) INTA PIRQA
> - PCI_BDF(2, 0, 1) INTA PIRQA
> - PCI_BDF(2, 0, 2) INTA PIRQA
> - PCI_BDF(2, 2, 0) INTB PIRQD
> - PCI_BDF(2, 2, 1) INTB PIRQD
> - PCI_BDF(2, 2, 2) INTB PIRQD
> - PCI_BDF(2, 2, 3) INTB PIRQD
> - PCI_BDF(2, 2, 4) INTB PIRQD
> - PCI_BDF(2, 4, 0) INTC PIRQC
> - PCI_BDF(2, 4, 1) INTC PIRQC
> - PCI_BDF(2, 6, 0) INTD PIRQB
> - PCI_BDF(2, 8, 0) INTA PIRQA
> - PCI_BDF(2, 8, 1) INTA PIRQA
> - PCI_BDF(2, 8, 2) INTA PIRQA
> - PCI_BDF(2, 8, 3) INTA PIRQA
> - PCI_BDF(2, 10, 0) INTB PIRQD
> - PCI_BDF(2, 10, 1) INTB PIRQD
> - PCI_BDF(2, 10, 2) INTB PIRQD
> - PCI_BDF(2, 10, 3) INTB PIRQD
> - PCI_BDF(2, 10, 4) INTB PIRQD
> - PCI_BDF(2, 12, 0) INTC PIRQC
> - PCI_BDF(2, 12, 1) INTC PIRQC
> - PCI_BDF(2, 12, 2) INTC PIRQC
> - PCI_BDF(2, 12, 3) INTC PIRQC
> - PCI_BDF(2, 12, 4) INTC PIRQC
> - >;
> + compatible = "intel,pch7";
> +
> + irq-router {
> + compatible = "intel,irq-router";
> + intel,pirq-config = "pci";
> + intel,pirq-link = <0x60 8>;
> + intel,pirq-mask = <0xcee0>;
> + intel,pirq-routing = <
> + /* TunnelCreek PCI devices */
> + PCI_BDF(0, 2, 0) INTA PIRQE
> + PCI_BDF(0, 3, 0) INTA PIRQF
> + PCI_BDF(0, 23, 0) INTA PIRQA
> + PCI_BDF(0, 23, 0) INTB PIRQB
> + PCI_BDF(0, 23, 0) INTC PIRQC
> + PCI_BDF(0, 23, 0) INTD PIRQD
> + PCI_BDF(0, 24, 0) INTA PIRQB
> + PCI_BDF(0, 24, 0) INTB PIRQC
> + PCI_BDF(0, 24, 0) INTC PIRQD
> + PCI_BDF(0, 24, 0) INTD PIRQA
> + PCI_BDF(0, 25, 0) INTA PIRQC
> + PCI_BDF(0, 25, 0) INTB PIRQD
> + PCI_BDF(0, 25, 0) INTC PIRQA
> + PCI_BDF(0, 25, 0) INTD PIRQB
> + PCI_BDF(0, 26, 0) INTA PIRQD
> + PCI_BDF(0, 26, 0) INTB PIRQA
> + PCI_BDF(0, 26, 0) INTC PIRQB
> + PCI_BDF(0, 26, 0) INTD PIRQC
> + PCI_BDF(0, 27, 0) INTA PIRQG
> + /*
> + * Topcliff PCI devices
> + *
> + * Note on the Crown Bay board, Topcliff
> + * chipset is connected to TunnelCreek
> + * PCIe port 0, so its bus number is 1
> + * for its PCIe port and 2 for its PCI
> + * devices per U-Boot current PCI bus
> + * enumeration algorithm.
> + */
> + PCI_BDF(1, 0, 0) INTA PIRQA
> + PCI_BDF(2, 0, 1) INTA PIRQA
> + PCI_BDF(2, 0, 2) INTA PIRQA
> + PCI_BDF(2, 2, 0) INTB PIRQD
> + PCI_BDF(2, 2, 1) INTB PIRQD
> + PCI_BDF(2, 2, 2) INTB PIRQD
> + PCI_BDF(2, 2, 3) INTB PIRQD
> + PCI_BDF(2, 2, 4) INTB PIRQD
> + PCI_BDF(2, 4, 0) INTC PIRQC
> + PCI_BDF(2, 4, 1) INTC PIRQC
> + PCI_BDF(2, 6, 0) INTD PIRQB
> + PCI_BDF(2, 8, 0) INTA PIRQA
> + PCI_BDF(2, 8, 1) INTA PIRQA
> + PCI_BDF(2, 8, 2) INTA PIRQA
> + PCI_BDF(2, 8, 3) INTA PIRQA
> + PCI_BDF(2, 10, 0) INTB PIRQD
> + PCI_BDF(2, 10, 1) INTB PIRQD
> + PCI_BDF(2, 10, 2) INTB PIRQD
> + PCI_BDF(2, 10, 3) INTB PIRQD
> + PCI_BDF(2, 10, 4) INTB PIRQD
> + PCI_BDF(2, 12, 0) INTC PIRQC
> + PCI_BDF(2, 12, 1) INTC PIRQC
> + PCI_BDF(2, 12, 2) INTC PIRQC
> + PCI_BDF(2, 12, 3) INTC PIRQC
> + PCI_BDF(2, 12, 4) INTC PIRQC
> + >;
> + };
> };
> };
>
[snip]
Regards,
Bin
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