[U-Boot] [PATCH v4 8/8] dm: x86: spi: Convert ICH SPI driver to driver model PCI API

[Bin Meng]

Hi Simon,

On Mon, Jan 18, 2016 at 3:44 PM, Bin Meng <bmeng.cn at gmail.com> wrote:
> Hi Simon,
>
> On Sun, Jan 17, 2016 at 7:44 AM, Simon Glass <sjg at chromium.org> wrote:
>> At present this SPI driver works by searching the PCI buses for its
>> peripheral. It also uses the legacy PCI API.
>>
>> In addition the driver has code to determine the type of Intel PCH that is
>> used (version 7 or version 9). Now that we have proper PCH drivers we can
>> use those to obtain the information we need.
>>
>> While the device tree has a node for the SPI peripheral it is not in the
>> right place. It should be on the PCI bus as a sub-peripheral of the LPC
>> device.
>>
>> Update the device tree files to show the SPI controller within the PCH, so
>> that PCI access works as expected.
>>
>> Signed-off-by: Simon Glass <sjg at chromium.org>
>> Reviewed-by: Bin Meng <bmeng.cn at gmail.com>
>> ---
>>
>> Changes in v4:
>> - Add BIOS_CTRL address for PCH9
>>
>> Changes in v3:
>> - Use the set_spi_protect() PCH method
>>
>> Changes in v2:
>> - Adjust code for earlier commits
>> - Move the SPI base code into the PCH drivers
>>
>>  arch/x86/cpu/coreboot/pci.c         |   3 +-
>>  arch/x86/cpu/irq.c                  |   7 +-
>>  arch/x86/cpu/ivybridge/bd82x6x.c    |  47 ++++++++++-
>>  arch/x86/dts/bayleybay.dts          | 160 +++++++++++++++++++-----------------
>>  arch/x86/dts/broadwell_som-6896.dts |  23 ++++--
>>  arch/x86/dts/chromebook_link.dts    |   5 +-
>>  arch/x86/dts/chromebox_panther.dts  |  33 ++++----
>>  arch/x86/dts/crownbay.dts           | 150 +++++++++++++++++----------------
>>  arch/x86/dts/galileo.dts            |  98 +++++++++++-----------
>>  arch/x86/dts/minnowmax.dts          | 158 ++++++++++++++++++-----------------
>>  arch/x86/dts/qemu-x86_i440fx.dts    |  26 +++---
>>  arch/x86/dts/qemu-x86_q35.dts       |  38 +++++----
>>  drivers/spi/ich.c                   | 152 ++++++++--------------------------
>>  13 files changed, 458 insertions(+), 442 deletions(-)
>>
>
> [snip]
>
>> diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
>> index 84231b3..ff739d4 100644
>> --- a/arch/x86/dts/crownbay.dts
>> +++ b/arch/x86/dts/crownbay.dts
>> @@ -72,17 +72,6 @@
>>                 stdout-path = "/serial";
>>         };
>>
>> -       spi {
>> -               #address-cells = <1>;
>> -               #size-cells = <0>;
>> -               compatible = "intel,ich-spi";
>> -               spi-flash at 0 {
>> -                       reg = <0>;
>> -                       compatible = "sst,25vf016b", "spi-flash";
>> -                       memory-map = <0xffe00000 0x00200000>;
>> -               };
>> -       };
>> -
>>         microcode {
>>                 update at 0 {
>>  #include "microcode/m0220661105_cv.dtsi"
>> @@ -105,6 +94,18 @@
>>                         u-boot,dm-pre-reloc;
>>                         reg = <0x0000b800 0x0 0x0 0x0 0x0>;
>>
>> +                       spi {
>> +                               #address-cells = <1>;
>> +                               #size-cells = <0>;
>> +                               compatible = "intel,ich-spi";
>> +                               spi-flash at 0 {
>> +                                       reg = <0>;
>> +                                       compatible = "sst,25vf016b",
>> +                                               "spi-flash";
>> +                                       memory-map = <0xffe00000 0x00200000>;
>> +                               };
>> +                       };
>> +
>
> Oops! This breaks Crown Bay from booting anymore. This should be moved
> after irq-router, to be a sub-node of pch.
>

Please squash this patch [1] in this one. It fixed the boot issue on
Crown Bay, as well as some clean up (adding a blank line between spi
sub-node and pch, for better reading).

[1] http://patchwork.ozlabs.org/patch/569478/

Regards,
Bin