[U-Boot] [PATCH] armv8: Enable CPUECTLR.SMPEN for data coherency

[Prabhakar Kushwaha]

Hi York,


> -----Original Message-----
> From: U-Boot [mailto:u-boot-bounces at lists.denx.de] On Behalf Of york sun
> Sent: Thursday, June 30, 2016 10:32 PM
> To: Qianyu Gong <qianyu.gong at nxp.com>; albert.u.boot at aribaud.net; u-
> boot at lists.denx.de; s.temerkhanov at gmail.com;
> yamada.masahiro at socionext.com
> Cc: Mingkai Hu <mingkai.hu at nxp.com>
> Subject: Re: [U-Boot] [PATCH] armv8: Enable CPUECTLR.SMPEN for data
> coherency
> 
> On 06/30/2016 02:03 AM, Gong Qianyu wrote:
> > From: Mingkai Hu <mingkai.hu at nxp.com>
> >
> > Data coherency is enabled only when the CPUECTLR.SMPEN bit is set. The
> > SMPEN bit should be set before enabling the data cache.
> > If not enabled, the cache is not coherent with other cores and data
> > corruption could occur.
> >
> > Signed-off-by: Mingkai Hu <mingkai.hu at nxp.com>
> > Signed-off-by: Gong Qianyu <Qianyu.Gong at nxp.com>
> >
> > diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
> > index 670e323..735dd67 100644
> > --- a/arch/arm/cpu/armv8/start.S
> > +++ b/arch/arm/cpu/armv8/start.S
> > @@ -81,6 +81,11 @@ reset:
> >   	msr	cpacr_el1, x0			/* Enable FP/SIMD */
> >   0:
> >
> > +	/* Enalbe SMPEN bit */
> > +	mrs     x0, S3_1_c15_c2_1               /* cpuactlr_el1 */
> > +	orr     x0, x0, #0x40
> > +	msr     S3_1_c15_c2_1, x0
> > +
> >   	/* Apply ARM core specific erratas */
> >   	bl	apply_core_errata
> >
> >
> 
> Qianyu,
> 
> I wonder what impact this patch has. Did you find it effective on A53 core?
> According to ARM documents, A57 and A72 seem don't care this bit.
> Quote
> 

I have seen big difference on LS1012A with A53 cores after enabling this bit.
If I don't enable this bit many IPs like SATA, SDHC show coherency issue. 

--prabhakar