[U-Boot] [PATCH v2 1/3] usb: rockchip-phy: implement USB2.0 phy control for Synopsys

[Ziyuan Xu]

From: Xu Ziyuan <xzy.xu at rock-chips.com>

So far, Rockchip SoCs have two kinds of USB2.0 phy, like Synopsys and
Innosilicon. This patch applys dwc2 usb driver framework to implement
phy_init and phy_off for Synopsys phy on Rockchip platform.

Signed-off-by: Ziyuan Xu <xzy.xu at rock-chips.com>

---

Changes in v2:
- Rename rk3288_usb_phy.c to rockchip_usb_syno_phy.c
- Rework the behaviour in otg_phy_init() and otg_phy_off()

 drivers/usb/phy/Makefile                |  1 +
 drivers/usb/phy/rockchip_usb_syno_phy.c | 48 +++++++++++++++++++++++++++++++++
 2 files changed, 49 insertions(+)
 create mode 100644 drivers/usb/phy/rockchip_usb_syno_phy.c

diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index 93d147e..8002a18 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -7,3 +7,4 @@
 
 obj-$(CONFIG_TWL4030_USB) += twl4030.o
 obj-$(CONFIG_OMAP_USB_PHY) += omap_usb_phy.o
+obj-$(CONFIG_ROCKCHIP_USB_SYNO_PHY) += rockchip_usb_syno_phy.o
diff --git a/drivers/usb/phy/rockchip_usb_syno_phy.c b/drivers/usb/phy/rockchip_usb_syno_phy.c
new file mode 100644
index 0000000..f79cb10
--- /dev/null
+++ b/drivers/usb/phy/rockchip_usb_syno_phy.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#include "../gadget/dwc2_udc_otg_priv.h"
+
+#define GRF_UOC0_CON0		0x320
+#define RESET_WRITE_ENA		BIT(28)
+#define PORT_RESET		BIT(12)
+#define PORT_NORMAL		(0 << 12)
+
+#define GRF_UOC0_CON2		0x328
+#define SOFT_CTRL_WRITE_ENA	BIT(18)
+#define SOFT_CTRL_ENABLE	BIT(2)
+
+#define GRF_UOC0_CON3		0x32c
+#define SUSPEND_SETTING		0x2A
+#define SUSPEND_WRITE_ENA	(0x3f << 16)
+
+
+void otg_phy_init(struct dwc2_udc *dev)
+{
+	/* disable software control */
+	writel(SOFT_CTRL_WRITE_ENA | (0 << 2),
+	       dev->pdata->regs_phy + GRF_UOC0_CON2);
+	/* reset otg port */
+	writel(RESET_WRITE_ENA | PORT_RESET,
+	       dev->pdata->regs_phy + GRF_UOC0_CON0);
+	mdelay(1);
+	writel(RESET_WRITE_ENA | PORT_NORMAL,
+	       dev->pdata->regs_phy + GRF_UOC0_CON0);
+	udelay(1);
+}
+
+void otg_phy_off(struct dwc2_udc *dev)
+{
+	/* enable software control */
+	writel(SOFT_CTRL_WRITE_ENA | SOFT_CTRL_ENABLE,
+	       dev->pdata->regs_phy + GRF_UOC0_CON2);
+	/* enter suspend */
+	writel(SUSPEND_WRITE_ENA | SUSPEND_SETTING,
+	       dev->pdata->regs_phy + GRF_UOC0_CON3);
+}
-- 
1.9.1