[U-Boot] [PATCH] armv8: Enable CPUECTLR.SMPEN for data coherency

Prabhakar Kushwaha prabhakar.kushwaha at nxp.com
Tue Jul 5 07:06:03 CEST 2016


> -----Original Message-----
> From: Edward L Swarthout
> Sent: Saturday, July 02, 2016 3:14 AM
> To: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>; york sun
> <york.sun at nxp.com>; Qianyu Gong <qianyu.gong at nxp.com>;
> albert.u.boot at aribaud.net; u-boot at lists.denx.de;
> s.temerkhanov at gmail.com; yamada.masahiro at socionext.com
> Cc: Mingkai Hu <mingkai.hu at nxp.com>
> Subject: RE: [U-Boot] [PATCH] armv8: Enable CPUECTLR.SMPEN for data
> coherency
> 
> From: Prabhakar Kushwaha
> 
> >> From: U-Boot [mailto:u-boot-bounces at lists.denx.de] On Behalf Of york
> >> On 06/30/2016 02:03 AM, Gong Qianyu wrote:
> >> > From: Mingkai Hu <mingkai.hu at nxp.com>
> >> >
> >> > Data coherency is enabled only when the CPUECTLR.SMPEN bit is set.
> >> > The SMPEN bit should be set before enabling the data cache.
> >> > If not enabled, the cache is not coherent with other cores and data
> >> > corruption could occur.
> >> >
> >> > +	/* Enalbe SMPEN bit */
> >> > +	mrs     x0, S3_1_c15_c2_1               /* cpuactlr_el1 */
> >> > +	orr     x0, x0, #0x40
> >> > +	msr     S3_1_c15_c2_1, x0
> >> > +
> >>
> >> I wonder what impact this patch has. Did you find it effective on A53 core?
> >> According to ARM documents, A57 and A72 seem don't care this bit.
> >
> >I have seen big difference on LS1012A with A53 cores after enabling this bit.
> >If I don't enable this bit many IPs like SATA, SDHC show coherency issue.
> 
> But LS1012A only has a single A53 core.
> The multicore part, LS1043A, sets this bit in the bootrom:
> 
>       34:	d539f221 	mrs	x1, s3_1_c15_c2_1
>       38:	b27a0021 	orr	x1, x1, #0x40
>       3c:	d519f221 	msr	s3_1_c15_c2_1, x1
> 

Bootrom team was under same impression like this bit not required for LS1012A. Hence they missed it. 

But as per Table 4-125 present in A53 TRM r0p4. This bit is required for hardware coherency.
" Set the SMPEN bit before enabling the caches, even if there is only one core in the system."

--prabhakar




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