[U-Boot] [U-Boot, v2] armv8: Enable CPUECTLR.SMPEN for coherency

[Tom Rini]

On Thu, Jul 07, 2016 at 12:22:12PM +0800, Qianyu Gong wrote:

> From: Mingkai Hu <mingkai.hu at nxp.com>
> 
> For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is
> set. The SMPEN bit should be set before enabling the data cache.
> If not enabled, the cache is not coherent with other cores and
> data corruption could occur.
> 
> For A57/A72, SMPEN bit enables the processor to receive instruction
> cache and TLB maintenance operations broadcast from other processors
> in the cluster. This bit should be set before enabling the caches and
> MMU, or performing any cache and TLB maintenance operations.
> 
> Signed-off-by: Mingkai Hu <mingkai.hu at nxp.com>
> Signed-off-by: Gong Qianyu <Qianyu.Gong at nxp.com>
> Reviewed-by: Masahiro Yamada <yamada.masahiro at socionext.com>

Applied to u-boot/master, thanks!

-- 
Tom
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