[U-Boot] [PATCH 2/4] Revert "arm: Replace v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL) with asm code"

[Sandy Patterson]

This reverts commit df120142f36b6ff8b12187b8860269763b2b3203.

Conflicts:
	arch/arm/cpu/armv7/cache_v7.c
	arch/arm/cpu/armv7/cache_v7_asm.S

Signed-off-by: Sandy Patterson <apatterson at sightlogix.com>
---

 arch/arm/cpu/armv7/cache_v7.c | 24 +++++++++++++++++++++---
 1 file changed, 21 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
index 85b0b0e..3e1ea2c 100644
--- a/arch/arm/cpu/armv7/cache_v7.c
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -10,10 +10,16 @@
 #include <asm/armv7.h>
 #include <asm/utils.h>
 
-#define ARMV7_DCACHE_INVAL_RANGE	1
-#define ARMV7_DCACHE_CLEAN_INVAL_RANGE	2
+#define ARMV7_DCACHE_INVAL_ALL		1
+#define ARMV7_DCACHE_CLEAN_INVAL_ALL	2
+#define ARMV7_DCACHE_INVAL_RANGE	3
+#define ARMV7_DCACHE_CLEAN_INVAL_RANGE	4
 
 #ifndef CONFIG_SYS_DCACHE_OFF
+
+/* Asm functions from cache_v7_asm.S */
+void v7_flush_dcache_all(void);
+
 static int check_cache_range(unsigned long start, unsigned long stop)
 {
 	int ok = 1;
@@ -31,6 +37,18 @@ static int check_cache_range(unsigned long start, unsigned long stop)
 	return ok;
 }
 
+/*
+ * Write the level and type you want to Cache Size Selection Register(CSSELR)
+ * to get size details from Current Cache Size ID Register(CCSIDR)
+ */
+static void set_csselr(u32 level, u32 type)
+{
+	u32 csselr = level << 1 | type;
+
+	/* Write to Cache Size Selection Register(CSSELR) */
+	asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr));
+}
+
 static u32 get_ccsidr(void)
 {
 	u32 ccsidr;
@@ -238,7 +256,7 @@ static void v7_inval_tlb(void)
 
 void invalidate_dcache_all(void)
 {
-	v7_invalidate_dcache_all();
+	v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL);
 
 	v7_outer_cache_inval_all();
 }
-- 
1.9.1